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| author | Wolfgang Denk <wd@denx.de> | 2007-06-20 18:14:24 +0200 |
|---|---|---|
| committer | Wolfgang Denk <wd@denx.de> | 2007-06-20 18:14:24 +0200 |
| commit | 83b4cfa3d629dff0264366263c5e94d9a50ad80b (patch) | |
| tree | ccc540cd7ff4f3684874e98ba91e53fa74312275 /board/lwmon5/lwmon5.c | |
| parent | 6b44466cdeabd54f9dabcd2f00d3a232a4b854a9 (diff) | |
| download | u-boot-imx-83b4cfa3d629dff0264366263c5e94d9a50ad80b.zip u-boot-imx-83b4cfa3d629dff0264366263c5e94d9a50ad80b.tar.gz u-boot-imx-83b4cfa3d629dff0264366263c5e94d9a50ad80b.tar.bz2 | |
Coding style cleanup. Refresh CHANGELOG.
Diffstat (limited to 'board/lwmon5/lwmon5.c')
| -rw-r--r-- | board/lwmon5/lwmon5.c | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/board/lwmon5/lwmon5.c b/board/lwmon5/lwmon5.c index 69b45ac..b303ec7 100644 --- a/board/lwmon5/lwmon5.c +++ b/board/lwmon5/lwmon5.c @@ -34,9 +34,9 @@ int board_early_init_f(void) u32 sdr0_pfc1, sdr0_pfc2; u32 reg; - /* PLB Write pipelining disabled. Denali Core workaround */ - mtdcr(plb0_acr, 0xDE000000); - mtdcr(plb1_acr, 0xDE000000); + /* PLB Write pipelining disabled. Denali Core workaround */ + mtdcr(plb0_acr, 0xDE000000); + mtdcr(plb1_acr, 0xDE000000); /*-------------------------------------------------------------------- * Setup the interrupt controller polarities, triggers, etc. @@ -86,9 +86,9 @@ int board_early_init_f(void) mtsdr(SDR0_PFC4, 0x80000000); /* PCI arbiter disabled */ - /* PCI Host Configuration disbaled */ + /* PCI Host Configuration disbaled */ mfsdr(sdr_pci0, reg); - reg = 0; + reg = 0; mtsdr(sdr_pci0, 0x00000000 | reg); gpio_write_bit(CFG_GPIO_FLASH_WP, 1); |