arm: Remove imx27lite, imx27_litekit and magnesium boards

These boards have not been converted to generic board by the deadline.
Remove them.

Signed-off-by: Simon Glass <sjg@chromium.org>

5 files changed, 0 insertions, 285 deletions

diff --git a/board/logicpd/imx27lite/Kconfig b/board/logicpd/imx27lite/Kconfig
deleted file mode 100644
index c7de2e3..0000000
--- a/board/logicpd/imx27lite/Kconfig
+++ /dev/null
@@ -1,31 +0,0 @@
-if TARGET_IMX27LITE
-
-config SYS_BOARD
-	default "imx27lite"
-
-config SYS_VENDOR
-	default "logicpd"
-
-config SYS_SOC
-	default "mx27"
-
-config SYS_CONFIG_NAME
-	default "imx27lite"
-
-endif
-
-if TARGET_MAGNESIUM
-
-config SYS_BOARD
-	default "imx27lite"
-
-config SYS_VENDOR
-	default "logicpd"
-
-config SYS_SOC
-	default "mx27"
-
-config SYS_CONFIG_NAME
-	default "magnesium"
-
-endif
diff --git a/board/logicpd/imx27lite/MAINTAINERS b/board/logicpd/imx27lite/MAINTAINERS
deleted file mode 100644
index a7b22ac..0000000
--- a/board/logicpd/imx27lite/MAINTAINERS
+++ /dev/null
@@ -1,12 +0,0 @@
-IMX27LITE BOARD
-M:	Wolfgang Denk <wd@denx.de>
-S:	Maintained
-F:	board/logicpd/imx27lite/
-F:	include/configs/imx27lite.h
-F:	configs/imx27lite_defconfig
-
-MAGNESIUM BOARD
-M:	Heiko Schocher <hs@denx.de>
-S:	Maintained
-F:	include/configs/magnesium.h
-F:	configs/magnesium_defconfig
diff --git a/board/logicpd/imx27lite/Makefile b/board/logicpd/imx27lite/Makefile
deleted file mode 100644
index 50a3da6..0000000
--- a/board/logicpd/imx27lite/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# (C) Copyright 2000-2004
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= imx27lite.o
-obj-y	+= lowlevel_init.o
diff --git a/board/logicpd/imx27lite/imx27lite.c b/board/logicpd/imx27lite/imx27lite.c
deleted file mode 100644
index 07b07a0..0000000
--- a/board/logicpd/imx27lite/imx27lite.c
+++ /dev/null
@@ -1,77 +0,0 @@
-/*
- * Copyright (C) 2007 Sascha Hauer, Pengutronix
- * Copyright (C) 2008,2009 Eric Jarrige <jorasse@users.sourceforge.net>
- * Copyright (C) 2009 Ilya Yanok <yanok@emcraft.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/gpio.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int board_init(void)
-{
-#if defined(CONFIG_SYS_NAND_LARGEPAGE)
-	struct system_control_regs *sc_regs =
-		(struct system_control_regs *)IMX_SYSTEM_CTL_BASE;
-#endif
-
-	gd->bd->bi_arch_number = MACH_TYPE_IMX27LITE;
-	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
-
-#ifdef CONFIG_MXC_UART
-	mx27_uart1_init_pins();
-#endif
-#ifdef CONFIG_FEC_MXC
-	mx27_fec_init_pins();
-	imx_gpio_mode((GPIO_PORTC | GPIO_OUT | GPIO_PUEN | GPIO_GPIO | 31));
-	gpio_set_value(GPIO_PORTC | 31, 1);
-#endif
-#ifdef CONFIG_MXC_MMC
-#if defined(CONFIG_MAGNESIUM)
-	mx27_sd1_init_pins();
-#else
-	mx27_sd2_init_pins();
-#endif
-#endif
-
-#if defined(CONFIG_SYS_NAND_LARGEPAGE)
-	/*
-	 * set in FMCR NF_FMS Bit(5) to 1
-	 * (NAND Flash with 2 Kbyte page size)
-	 */
-	writel(readl(&sc_regs->fmcr) | (1 << 5), &sc_regs->fmcr);
-#endif
-	return 0;
-}
-
-int dram_init(void)
-{
-	/* dram_init must store complete ramsize in gd->ram_size */
-	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
-				PHYS_SDRAM_1_SIZE);
-	return 0;
-}
-
-void dram_init_banksize(void)
-{
-	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
-	gd->bd->bi_dram[0].size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
-			PHYS_SDRAM_1_SIZE);
-#if CONFIG_NR_DRAM_BANKS > 1
-	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
-	gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2,
-			PHYS_SDRAM_2_SIZE);
-#endif
-}
-
-int checkboard(void)
-{
-	puts("Board: ");
-	puts(CONFIG_BOARDNAME);
-	return 0;
-}
diff --git a/board/logicpd/imx27lite/lowlevel_init.S b/board/logicpd/imx27lite/lowlevel_init.S
deleted file mode 100644
index 9cb702f..0000000
--- a/board/logicpd/imx27lite/lowlevel_init.S
+++ /dev/null
@@ -1,156 +0,0 @@
-/*
- * For clock initialization, see chapter 3 of the "MCIMX27 Multimedia
- * Applications Processor Reference Manual, Rev. 0.2".
- *
- * (C) Copyright 2008 Eric Jarrige <eric.jarrige@armadeus.org>
- * (C) Copyright 2009 Ilya Yanok <yanok@emcraft.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-
-#include <config.h>
-#include <asm/macro.h>
-#include <asm/arch/imx-regs.h>
-#include <generated/asm-offsets.h>
-
-SOC_ESDCTL_BASE_W:	.word	IMX_ESD_BASE
-SOC_SI_ID_REG_W:	.word	IMX_SYSTEM_CTL_BASE
-SDRAM_ESDCFG_T1_W:	.word	SDRAM_ESDCFG_REGISTER_VAL(0)
-SDRAM_ESDCFG_T2_W:	.word	SDRAM_ESDCFG_REGISTER_VAL(3)
-SDRAM_PRECHARGE_CMD_W:	.word	(ESDCTL_SDE | ESDCTL_SMODE_PRECHARGE | \
-				 ESDCTL_ROW13 | ESDCTL_COL10)
-SDRAM_AUTOREF_CMD_W:	.word	(ESDCTL_SDE | ESDCTL_SMODE_AUTO_REF | \
-				 ESDCTL_ROW13 | ESDCTL_COL10)
-SDRAM_LOADMODE_CMD_W:	.word	(ESDCTL_SDE | ESDCTL_SMODE_LOAD_MODE | \
-				 ESDCTL_ROW13 | ESDCTL_COL10)
-SDRAM_NORMAL_CMD_W:	.word	SDRAM_ESDCTL_REGISTER_VAL
-
-.macro init_aipi
-	/*
-	 * setup AIPI1 and AIPI2
-	 */
-	write32 AIPI1_PSR0, AIPI1_PSR0_VAL
-	write32 AIPI1_PSR1, AIPI1_PSR1_VAL
-	write32 AIPI2_PSR0, AIPI2_PSR0_VAL
-	write32 AIPI2_PSR1, AIPI2_PSR1_VAL
-
-.endm /* init_aipi */
-
-.macro init_clock
-	ldr r0, =CSCR
-	/* disable MPLL/SPLL first */
-	ldr r1, [r0]
-	bic r1, r1, #(CSCR_MPEN|CSCR_SPEN)
-	str r1, [r0]
-
-	write32 MPCTL0, MPCTL0_VAL
-	write32 SPCTL0, SPCTL0_VAL
-
-	write32 CSCR, CSCR_VAL | CSCR_MPLL_RESTART | CSCR_SPLL_RESTART
-
-	/*
-	 * add some delay here
-	 */
-	wait_timer 0x1000
-
-	/* peripheral clock divider */
-	write32 PCDR0, PCDR0_VAL
-	write32 PCDR1, PCDR1_VAL
-
-	/* Configure PCCR0 and PCCR1 */
-	write32 PCCR0, PCCR0_VAL
-	write32 PCCR1, PCCR1_VAL
-
-.endm /* init_clock */
-
-.macro sdram_init
-	ldr r0, SOC_ESDCTL_BASE_W
-	mov r2, #PHYS_SDRAM_1
-
-	/* Do initial reset */
-	mov r1, #ESDMISC_MDDR_DL_RST
-	str r1, [r0, #ESDMISC_ROF]
-
-	/* Hold for more than 200ns */
-	wait_timer 0x10000
-
-	/* Activate LPDDR iface */
-	mov r1, #ESDMISC_MDDREN
-	str r1, [r0, #ESDMISC_ROF]
-
-	/* Check The chip version TO1 or TO2 */
-	ldr r1, SOC_SI_ID_REG_W
-	ldr r1, [r1]
-	ands r1, r1, #0xF0000000
-	/* add Latency on CAS only for TO2 */
-	ldreq r1, SDRAM_ESDCFG_T2_W
-	ldrne r1, SDRAM_ESDCFG_T1_W
-	str r1, [r0, #ESDCFG0_ROF]
-
-	/* Run initialization sequence */
-	ldr r1, SDRAM_PRECHARGE_CMD_W
-	str r1, [r0, #ESDCTL0_ROF]
-	ldr r1, [r2, #SDRAM_ALL_VAL]
-
-	ldr r1, SDRAM_AUTOREF_CMD_W
-	str r1, [r0, #ESDCTL0_ROF]
-	ldr r1, [r2, #SDRAM_ALL_VAL]
-	ldr r1, [r2, #SDRAM_ALL_VAL]
-
-	ldr r1, SDRAM_LOADMODE_CMD_W
-	str r1, [r0, #ESDCTL0_ROF]
-	ldrb r1, [r2, #SDRAM_MODE_REGISTER_VAL]
-	add r3, r2, #SDRAM_EXT_MODE_REGISTER_VAL
-	ldrb r1, [r3]
-
-	ldr r1, SDRAM_NORMAL_CMD_W
-	str r1, [r0, #ESDCTL0_ROF]
-
-#if (CONFIG_NR_DRAM_BANKS > 1)
-	/* 2nd sdram */
-	mov r2, #PHYS_SDRAM_2
-
-	/* Check The chip version TO1 or TO2 */
-	ldr r1, SOC_SI_ID_REG_W
-	ldr r1, [r1]
-	ands r1, r1, #0xF0000000
-	/* add Latency on CAS only for TO2 */
-	ldreq r1, SDRAM_ESDCFG_T2_W
-	ldrne r1, SDRAM_ESDCFG_T1_W
-	str r1, [r0, #ESDCFG1_ROF]
-
-	/* Run initialization sequence */
-	ldr r1, SDRAM_PRECHARGE_CMD_W
-	str r1, [r0, #ESDCTL1_ROF]
-	ldr r1, [r2, #SDRAM_ALL_VAL]
-
-	ldr r1, SDRAM_AUTOREF_CMD_W
-	str r1, [r0, #ESDCTL1_ROF]
-	ldr r1, [r2, #SDRAM_ALL_VAL]
-	ldr r1, [r2, #SDRAM_ALL_VAL]
-
-	ldr r1, SDRAM_LOADMODE_CMD_W
-	str r1, [r0, #ESDCTL1_ROF]
-	ldrb r1, [r2, #SDRAM_MODE_REGISTER_VAL]
-	add r3, r2, #SDRAM_EXT_MODE_REGISTER_VAL
-	ldrb r1, [r3]
-
-	ldr r1, SDRAM_NORMAL_CMD_W
-	str r1, [r0, #ESDCTL1_ROF]
-#endif  /* CONFIG_NR_DRAM_BANKS > 1 */
-
-.endm /* sdram_init */
-
-.globl	lowlevel_init
-lowlevel_init:
-
-	mov	r10, lr
-
-	init_aipi
-
-	init_clock
-
-	sdram_init
-
-	mov	pc,r10