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authorProdyut Hazarika <phazarika@amcc.com>2008-08-20 09:38:51 -0700
committerStefan Roese <sr@denx.de>2008-08-21 10:31:16 +0200
commit079589bcfb24ba11068460276a3cc9549ab5346f (patch)
tree85b33c32aaafdedac703834bd763bbf25695f456 /board/lantec
parentba37aa03287c5483c61c0a3e320c8888bee0143a (diff)
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ppc4xx: Optimize PLB4 Arbiter and Memory Queue settings for PPC440SP/SPe,
PPC405EX and PPC460EX/GT/SX - Read pipeline depth set to 4 for PPC440SP/SPE, PPC405EX, PPC460EX/GT/SX processors - Moved PLB4 Arbiter register definitions to ppc4xx.h since it is shared across processors (405 and 440/460) - Optimize Memory Queue settings for PPC440SP/SPE and PPC460EX/GT/SX processors - Add register bit definitions for Memory Queue Configuration registers Signed-off-by: Prodyut Hazarika <phazarika@amcc.com> Signed-off-by: Stefan Roese <sr@denx.de>
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