Merge git://git.denx.de/u-boot into x1

Conflicts:

	drivers/usb/usb_ohci.c

8 files changed, 1371 insertions, 0 deletions

diff --git a/board/keymile/common/common.c b/board/keymile/common/common.c
new file mode 100644
index 0000000..a4cf24c
--- /dev/null
+++ b/board/keymile/common/common.c
@@ -0,0 +1,523 @@
+/*
+ * (C) Copyright 2008
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc8260.h>
+#include <ioports.h>
+#include <malloc.h>
+#include <hush.h>
+
+#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
+#include <libfdt.h>
+#endif
+
+#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C)
+#include <i2c.h>
+#endif
+#include <asm/io.h>
+
+extern int i2c_soft_read_pin (void);
+
+int ivm_calc_crc (unsigned char *buf, int len)
+{
+	const unsigned short crc_tab[16] = {
+		0x0000, 0xCC01, 0xD801, 0x1400,
+		0xF001, 0x3C00, 0x2800, 0xE401,
+		0xA001, 0x6C00, 0x7800, 0xB401,
+		0x5000, 0x9C01, 0x8801, 0x4400};
+
+	unsigned short crc     = 0;   /* final result */
+	unsigned short r1      = 0;   /* temp */
+	unsigned char  byte    = 0;   /* input buffer */
+	int	i;
+
+	/* calculate CRC from array data */
+	for (i = 0; i < len; i++) {
+		byte = buf[i];
+
+		/* lower 4 bits */
+		r1 = crc_tab[crc & 0xF];
+		crc = ((crc) >> 4) & 0x0FFF;
+		crc = crc ^ r1 ^ crc_tab[byte & 0xF];
+
+		/* upper 4 bits */
+		r1 = crc_tab[crc & 0xF];
+		crc = (crc >> 4) & 0x0FFF;
+		crc = crc ^ r1 ^ crc_tab[(byte >> 4) & 0xF];
+	}
+	return crc;
+}
+
+static int  ivm_set_value (char *name, char *value)
+{
+	char tempbuf[256];
+
+	if (value != NULL) {
+		sprintf (tempbuf, "%s=%s", name, value);
+		return set_local_var (tempbuf, 0);
+	} else {
+		unset_local_var (name);
+	}
+	return 0;
+}
+
+static int ivm_get_value (unsigned char *buf, int len, char *name, int off,
+				int check)
+{
+	unsigned short	val;
+	unsigned char	valbuf[30];
+
+	if ((buf[off + 0] != buf[off + 2]) &&
+	    (buf[off + 2] != buf[off + 4])) {
+		printf ("%s Error corrupted %s\n", __FUNCTION__, name);
+		val = -1;
+	} else {
+		val = buf[off + 0] + (buf[off + 1] << 8);
+		if ((val == 0) && (check == 1))
+			val = -1;
+	}
+	sprintf ((char *)valbuf, "%x", val);
+	ivm_set_value (name, (char *)valbuf);
+	return val;
+}
+
+#define INVENTORYBLOCKSIZE	0x100
+#define INVENTORYDATAADDRESS	0x21
+#define INVENTORYDATASIZE	(INVENTORYBLOCKSIZE - INVENTORYDATAADDRESS - 3)
+
+#define IVM_POS_SHORT_TEXT		0
+#define IVM_POS_MANU_ID			1
+#define IVM_POS_MANU_SERIAL		2
+#define IVM_POS_PART_NUMBER		3
+#define IVM_POS_BUILD_STATE		4
+#define IVM_POS_SUPPLIER_PART_NUMBER	5
+#define IVM_POS_DELIVERY_DATE		6
+#define IVM_POS_SUPPLIER_BUILD_STATE	7
+#define IVM_POS_CUSTOMER_ID		8
+#define IVM_POS_CUSTOMER_PROD_ID	9
+#define IVM_POS_HISTORY			10
+#define IVM_POS_SYMBOL_ONLY		11
+
+static char convert_char (char c)
+{
+	return (c < ' ' || c > '~') ? '.' : c;
+}
+
+static int ivm_findinventorystring (int type,
+					unsigned char* const string,
+					unsigned long maxlen,
+					unsigned char *buf)
+{
+	int xcode = 0;
+	unsigned long cr = 0;
+	unsigned long addr = INVENTORYDATAADDRESS;
+	unsigned long size = 0;
+	unsigned long nr = type;
+	int stop = 0; 	/* stop on semicolon */
+
+	memset(string, '\0', maxlen);
+	switch (type) {
+		case IVM_POS_SYMBOL_ONLY:
+			nr = 0;
+			stop= 1;
+		break;
+		default:
+			nr = type;
+			stop = 0;
+	}
+
+	/* Look for the requested number of CR. */
+	while ((cr != nr) && (addr < INVENTORYDATASIZE)) {
+		if ((buf[addr] == '\r')) {
+			cr++;
+		}
+		addr++;
+	}
+
+	/* the expected number of CR was found until the end of the IVM
+	 *  content --> fill string */
+	if (addr < INVENTORYDATASIZE) {
+		/* Copy the IVM string in the corresponding string */
+		for (; (buf[addr] != '\r')			&&
+			((buf[addr] != ';') ||  (!stop))	&&
+			(size < (maxlen - 1)			&&
+			(addr < INVENTORYDATASIZE)); addr++)
+		{
+			size += sprintf((char *)string + size, "%c",
+						convert_char (buf[addr]));
+		}
+
+		/* copy phase is done: check if everything is ok. If not,
+		 * the inventory data is most probably corrupted: tell
+		 * the world there is a problem! */
+		if (addr == INVENTORYDATASIZE) {
+			xcode = -1;
+			printf ("Error end of string not found\n");
+		} else if ((size >= (maxlen - 1)) &&
+			   (buf[addr] != '\r')) {
+			xcode = -1;
+			printf ("string too long till next CR\n");
+		}
+	} else {
+		/* some CR are missing...
+		 * the inventory data is most probably corrupted */
+		xcode = -1;
+		printf ("not enough cr found\n");
+	}
+	return xcode;
+}
+
+#define GET_STRING(name, which, len) \
+	if (ivm_findinventorystring (which, valbuf, len, buf) == 0) { \
+		ivm_set_value (name, (char *)valbuf); \
+	}
+
+static int ivm_check_crc (unsigned char *buf, int block)
+{
+	unsigned long	crc;
+	unsigned long	crceeprom;
+
+	crc = ivm_calc_crc (buf, CONFIG_SYS_IVM_EEPROM_PAGE_LEN - 2);
+	crceeprom = (buf[CONFIG_SYS_IVM_EEPROM_PAGE_LEN - 1] + \
+			buf[CONFIG_SYS_IVM_EEPROM_PAGE_LEN - 2] * 256);
+	if (crc != crceeprom) {
+		printf ("Error CRC Block: %d EEprom: calculated: %lx EEprom: %lx\n",
+			block, crc, crceeprom);
+		return -1;
+	}
+	return 0;
+}
+
+static int ivm_analyze_block2 (unsigned char *buf, int len)
+{
+	unsigned char	valbuf[CONFIG_SYS_IVM_EEPROM_PAGE_LEN];
+	unsigned long	count;
+
+	/* IVM_MacAddress */
+	sprintf ((char *)valbuf, "%02X:%02X:%02X:%02X:%02X:%02X",
+			buf[1],
+			buf[2],
+			buf[3],
+			buf[4],
+			buf[5],
+			buf[6]);
+	ivm_set_value ("IVM_MacAddress", (char *)valbuf);
+	if (getenv ("ethaddr") == NULL)
+		setenv ((char *)"ethaddr", (char *)valbuf);
+	/* IVM_MacCount */
+	count = (buf[10] << 24) +
+		   (buf[11] << 16) +
+		   (buf[12] << 8)  +
+		    buf[13];
+	if (count == 0xffffffff)
+		count = 1;
+	sprintf ((char *)valbuf, "%lx", count);
+	ivm_set_value ("IVM_MacCount", (char *)valbuf);
+	return 0;
+}
+
+int ivm_analyze_eeprom (unsigned char *buf, int len)
+{
+	unsigned short	val;
+	unsigned char	valbuf[CONFIG_SYS_IVM_EEPROM_PAGE_LEN];
+	unsigned char	*tmp;
+
+	if (ivm_check_crc (buf, 0) != 0)
+		return -1;
+
+	ivm_get_value (buf, CONFIG_SYS_IVM_EEPROM_PAGE_LEN, "IVM_BoardId", 0, 1);
+	val = ivm_get_value (buf, CONFIG_SYS_IVM_EEPROM_PAGE_LEN, "IVM_HWKey", 6, 1);
+	if (val != 0xffff) {
+		sprintf ((char *)valbuf, "%x", ((val /100) % 10));
+		ivm_set_value ("IVM_HWVariant", (char *)valbuf);
+		sprintf ((char *)valbuf, "%x", (val % 100));
+		ivm_set_value ("IVM_HWVersion", (char *)valbuf);
+	}
+	ivm_get_value (buf, CONFIG_SYS_IVM_EEPROM_PAGE_LEN, "IVM_Functions", 12, 0);
+
+	GET_STRING("IVM_Symbol", IVM_POS_SYMBOL_ONLY, 8)
+	GET_STRING("IVM_DeviceName", IVM_POS_SHORT_TEXT, 64)
+	tmp = (unsigned char *) getenv("IVM_DeviceName");
+	if (tmp) {
+		int	len = strlen ((char *)tmp);
+		int	i = 0;
+
+		while (i < len) {
+			if (tmp[i] == ';') {
+				ivm_set_value ("IVM_ShortText", (char *)&tmp[i + 1]);
+				break;
+			}
+			i++;
+		}
+		if (i >= len)
+			ivm_set_value ("IVM_ShortText", NULL);
+	} else {
+		ivm_set_value ("IVM_ShortText", NULL);
+	}
+	GET_STRING("IVM_ManufacturerID", IVM_POS_MANU_ID, 32)
+	GET_STRING("IVM_ManufacturerSerialNumber", IVM_POS_MANU_SERIAL, 20)
+	GET_STRING("IVM_ManufacturerPartNumber", IVM_POS_PART_NUMBER, 32)
+	GET_STRING("IVM_ManufacturerBuildState", IVM_POS_BUILD_STATE, 32)
+	GET_STRING("IVM_SupplierPartNumber", IVM_POS_SUPPLIER_PART_NUMBER, 32)
+	GET_STRING("IVM_DelieveryDate", IVM_POS_DELIVERY_DATE, 32)
+	GET_STRING("IVM_SupplierBuildState", IVM_POS_SUPPLIER_BUILD_STATE, 32)
+	GET_STRING("IVM_CustomerID", IVM_POS_CUSTOMER_ID, 32)
+	GET_STRING("IVM_CustomerProductID", IVM_POS_CUSTOMER_PROD_ID, 32)
+
+	if (ivm_check_crc (&buf[CONFIG_SYS_IVM_EEPROM_PAGE_LEN * 2], 2) != 0)
+		return -2;
+	ivm_analyze_block2 (&buf[CONFIG_SYS_IVM_EEPROM_PAGE_LEN * 2], CONFIG_SYS_IVM_EEPROM_PAGE_LEN);
+
+	return 0;
+}
+
+int ivm_read_eeprom (void)
+{
+	I2C_MUX_DEVICE *dev = NULL;
+	uchar i2c_buffer[CONFIG_SYS_IVM_EEPROM_MAX_LEN];
+	uchar	*buf;
+	unsigned dev_addr = CONFIG_SYS_IVM_EEPROM_ADR;
+
+	/* First init the Bus, select the Bus */
+#if defined(CONFIG_SYS_I2C_IVM_BUS)
+	dev = i2c_mux_ident_muxstring ((uchar *)CONFIG_SYS_I2C_IVM_BUS);
+#else
+	buf = (unsigned char *) getenv ("EEprom_ivm");
+	if (buf != NULL)
+		dev = i2c_mux_ident_muxstring (buf);
+#endif
+	if (dev == NULL) {
+		printf ("Error couldnt add Bus for IVM\n");
+		return -1;
+	}
+	i2c_set_bus_num (dev->busid);
+
+	buf = (unsigned char *) getenv ("EEprom_ivm_addr");
+	if (buf != NULL)
+		dev_addr = simple_strtoul ((char *)buf, NULL, 16);
+
+	if (eeprom_read (dev_addr, 0, i2c_buffer, CONFIG_SYS_IVM_EEPROM_MAX_LEN) != 0) {
+		printf ("Error reading EEprom\n");
+		return -2;
+	}
+
+	return ivm_analyze_eeprom (i2c_buffer, CONFIG_SYS_IVM_EEPROM_MAX_LEN);
+}
+
+#if defined(CONFIG_SYS_I2C_INIT_BOARD)
+#define DELAY_ABORT_SEQ		62
+#define DELAY_HALF_PERIOD	(500 / (CONFIG_SYS_I2C_SPEED / 1000))
+
+#if defined(CONFIG_MGCOGE)
+#define SDA_MASK	0x00010000
+#define SCL_MASK	0x00020000
+static void set_pin (int state, unsigned long mask)
+{
+	volatile ioport_t *iop = ioport_addr ((immap_t *)CONFIG_SYS_IMMR, 3);
+
+	if (state)
+		iop->pdat |= (mask);
+	else
+		iop->pdat &= ~(mask);
+
+	iop->pdir |= (mask);
+}
+
+static int get_pin (unsigned long mask)
+{
+	volatile ioport_t *iop = ioport_addr ((immap_t *)CONFIG_SYS_IMMR, 3);
+
+	iop->pdir &= ~(mask);
+	return (0 != (iop->pdat & (mask)));
+}
+
+static void set_sda (int state)
+{
+	set_pin (state, SDA_MASK);
+}
+
+static void set_scl (int state)
+{
+	set_pin (state, SCL_MASK);
+}
+
+static int get_sda (void)
+{
+	return get_pin (SDA_MASK);
+}
+
+static int get_scl (void)
+{
+	return get_pin (SCL_MASK);
+}
+
+#if defined(CONFIG_HARD_I2C)
+static void setports (int gpio)
+{
+	volatile ioport_t *iop = ioport_addr ((immap_t *)CONFIG_SYS_IMMR, 3);
+
+	if (gpio) {
+		iop->ppar &= ~(SDA_MASK | SCL_MASK);
+		iop->podr &= ~(SDA_MASK | SCL_MASK);
+	} else {
+		iop->ppar |= (SDA_MASK | SCL_MASK);
+		iop->pdir &= ~(SDA_MASK | SCL_MASK);
+		iop->podr |= (SDA_MASK | SCL_MASK);
+	}
+}
+#endif
+#endif
+
+#if defined(CONFIG_MGSUVD)
+static void set_sda (int state)
+{
+	I2C_SDA(state);
+}
+
+static void set_scl (int state)
+{
+	I2C_SCL(state);
+}
+
+static int get_sda (void)
+{
+	return I2C_READ;
+}
+
+static int get_scl (void)
+{
+	int	val;
+
+	*(unsigned short *)(I2C_BASE_DIR) &=  ~SCL_CONF;
+	udelay (1);
+	val = *(unsigned char *)(I2C_BASE_PORT);
+
+	return ((val & SCL_BIT) == SCL_BIT);
+}
+
+#endif
+
+static void writeStartSeq (void)
+{
+	set_sda (1);
+	udelay (DELAY_HALF_PERIOD);
+	set_scl (1);
+	udelay (DELAY_HALF_PERIOD);
+	set_sda (0);
+	udelay (DELAY_HALF_PERIOD);
+	set_scl (0);
+	udelay (DELAY_HALF_PERIOD);
+}
+
+/* I2C is a synchronous protocol and resets of the processor in the middle
+   of an access can block the I2C Bus until a powerdown of the full unit is
+   done. This function toggles the SCL until the SCL and SCA line are
+   released, but max. 16 times, after this a I2C start-sequence is sent.
+   This I2C Deblocking mechanism was developed by Keymile in association
+   with Anatech and Atmel in 1998.
+ */
+static int i2c_make_abort (void)
+{
+	int	scl_state = 0;
+	int	sda_state = 0;
+	int	i = 0;
+	int	ret = 0;
+
+	if (!get_sda ()) {
+		ret = -1;
+		while (i < 16) {
+			i++;
+			set_scl (0);
+			udelay (DELAY_ABORT_SEQ);
+			set_scl (1);
+			udelay (DELAY_ABORT_SEQ);
+			scl_state = get_scl ();
+			sda_state = get_sda ();
+			if (scl_state && sda_state) {
+				ret = 0;
+				break;
+			}
+		}
+	}
+	if (ret == 0) {
+		for (i =0; i < 5; i++) {
+			writeStartSeq ();
+		}
+	}
+	get_sda ();
+	return ret;
+}
+
+/**
+ * i2c_init_board - reset i2c bus. When the board is powercycled during a
+ * bus transfer it might hang; for details see doc/I2C_Edge_Conditions.
+ */
+void i2c_init_board(void)
+{
+#if defined(CONFIG_HARD_I2C)
+	volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR ;
+	volatile i2c8260_t *i2c	= (i2c8260_t *)&immap->im_i2c;
+
+	/* disable I2C controller first, otherwhise it thinks we want to    */
+	/* talk to the slave port...                                        */
+	i2c->i2c_i2mod &= ~0x01;
+
+	/* Set the PortPins to GPIO */
+	setports (1);
+#endif
+
+	/* Now run the AbortSequence() */
+	i2c_make_abort ();
+
+#if defined(CONFIG_HARD_I2C)
+	/* Set the PortPins back to use for I2C */
+	setports (0);
+#endif
+}
+#endif
+
+#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
+int fdt_set_node_and_value (void *blob,
+				char *nodename,
+				char *regname,
+				void *var,
+				int size)
+{
+	int ret = 0;
+	int nodeoffset = 0;
+
+	nodeoffset = fdt_path_offset (blob, nodename);
+	if (nodeoffset >= 0) {
+		ret = fdt_setprop (blob, nodeoffset, regname, var,
+					size);
+		if (ret < 0)
+			printf("ft_blob_update(): cannot set %s/%s "
+				"property err:%s\n", nodename, regname,
+				fdt_strerror (ret));
+	} else {
+		printf("ft_blob_update(): cannot find %s node "
+			"err:%s\n", nodename, fdt_strerror (nodeoffset));
+	}
+	return ret;
+}
+#endif
diff --git a/board/keymile/mgcoge/Makefile b/board/keymile/mgcoge/Makefile
new file mode 100644
index 0000000..0cad821
--- /dev/null
+++ b/board/keymile/mgcoge/Makefile
@@ -0,0 +1,53 @@
+#
+# (C) Copyright 2001-2007
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../common)
+endif
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS	:= $(BOARD).o ../common/common.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/keymile/mgcoge/config.mk b/board/keymile/mgcoge/config.mk
new file mode 100644
index 0000000..143bc9f
--- /dev/null
+++ b/board/keymile/mgcoge/config.mk
@@ -0,0 +1,24 @@
+#
+# (C) Copyright 2007
+# Heiko Schocher, DENX Software Engineering, hs@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+TEXT_BASE = 0xFE000000
diff --git a/board/keymile/mgcoge/mgcoge.c b/board/keymile/mgcoge/mgcoge.c
new file mode 100644
index 0000000..6dda920
--- /dev/null
+++ b/board/keymile/mgcoge/mgcoge.c
@@ -0,0 +1,349 @@
+/*
+ * (C) Copyright 2007 - 2008
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc8260.h>
+#include <ioports.h>
+#include <malloc.h>
+#include <asm/io.h>
+
+#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
+#include <libfdt.h>
+#endif
+
+#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C)
+#include <i2c.h>
+#endif
+
+extern int ivm_read_eeprom (void);
+/*
+ * I/O Port configuration table
+ *
+ * if conf is 1, then that port pin will be configured at boot time
+ * according to the five values podr/pdir/ppar/psor/pdat for that entry
+ */
+const iop_conf_t iop_conf_tab[4][32] = {
+
+    /* Port A */
+    {	/*	      conf      ppar psor pdir podr pdat */
+	/* PA31 */ { 0,          0,   0,   0,   0,   0 }, /* PA31            */
+	/* PA30 */ { 0,          0,   0,   0,   0,   0 }, /* PA30            */
+	/* PA29 */ { 0,          0,   0,   0,   0,   0 }, /* PA29            */
+	/* PA28 */ { 0,          0,   0,   0,   0,   0 }, /* PA28            */
+	/* PA27 */ { 0,          0,   0,   0,   0,   0 }, /* PA27            */
+	/* PA26 */ { 0,          0,   0,   0,   0,   0 }, /* PA26            */
+	/* PA25 */ { 0,          0,   0,   0,   0,   0 }, /* PA25            */
+	/* PA24 */ { 0,          0,   0,   0,   0,   0 }, /* PA24            */
+	/* PA23 */ { 0,          0,   0,   0,   0,   0 }, /* PA23            */
+	/* PA22 */ { 0,          0,   0,   0,   0,   0 }, /* PA22            */
+	/* PA21 */ { 0,          0,   0,   0,   0,   0 }, /* PA21            */
+	/* PA20 */ { 0,          0,   0,   0,   0,   0 }, /* PA20            */
+	/* PA19 */ { 0,          0,   0,   0,   0,   0 }, /* PA19            */
+	/* PA18 */ { 0,          0,   0,   0,   0,   0 }, /* PA18            */
+	/* PA17 */ { 0,          0,   0,   0,   0,   0 }, /* PA17            */
+	/* PA16 */ { 0,          0,   0,   0,   0,   0 }, /* PA16            */
+	/* PA15 */ { 0,          0,   0,   0,   0,   0 }, /* PA15            */
+	/* PA14 */ { 0,          0,   0,   0,   0,   0 }, /* PA14            */
+	/* PA13 */ { 0,          0,   0,   0,   0,   0 }, /* PA13            */
+	/* PA12 */ { 0,          0,   0,   0,   0,   0 }, /* PA12            */
+	/* PA11 */ { 0,          0,   0,   0,   0,   0 }, /* PA11            */
+	/* PA10 */ { 0,          0,   0,   0,   0,   0 }, /* PA10            */
+	/* PA9  */ { 1,          1,   0,   1,   0,   0 }, /* SMC2 TxD        */
+	/* PA8  */ { 1,          1,   0,   0,   0,   0 }, /* SMC2 RxD        */
+	/* PA7  */ { 0,          0,   0,   0,   0,   0 }, /* PA7             */
+	/* PA6  */ { 0,          0,   0,   0,   0,   0 }, /* PA6             */
+	/* PA5  */ { 0,          0,   0,   0,   0,   0 }, /* PA5             */
+	/* PA4  */ { 0,          0,   0,   0,   0,   0 }, /* PA4             */
+	/* PA3  */ { 0,          0,   0,   0,   0,   0 }, /* PA3             */
+	/* PA2  */ { 0,          0,   0,   0,   0,   0 }, /* PA2             */
+	/* PA1  */ { 0,          0,   0,   0,   0,   0 }, /* PA1             */
+	/* PA0  */ { 0,          0,   0,   0,   0,   0 }  /* PA0             */
+    },
+
+    /* Port B */
+    {   /*	      conf      ppar psor pdir podr pdat */
+	/* PB31 */ { 0,          0,   0,   0,   0,   0 }, /* PB31            */
+	/* PB30 */ { 0,          0,   0,   0,   0,   0 }, /* PB30            */
+	/* PB29 */ { 0,          0,   0,   0,   0,   0 }, /* PB29            */
+	/* PB28 */ { 0,          0,   0,   0,   0,   0 }, /* PB28            */
+	/* PB27 */ { 0,          0,   0,   0,   0,   0 }, /* PB27            */
+	/* PB26 */ { 0,          0,   0,   0,   0,   0 }, /* PB26            */
+	/* PB25 */ { 0,          0,   0,   0,   0,   0 }, /* PB25            */
+	/* PB24 */ { 0,          0,   0,   0,   0,   0 }, /* PB24            */
+	/* PB23 */ { 0,          0,   0,   0,   0,   0 }, /* PB23            */
+	/* PB22 */ { 0,          0,   0,   0,   0,   0 }, /* PB22            */
+	/* PB21 */ { 0,          0,   0,   0,   0,   0 }, /* PB21            */
+	/* PB20 */ { 0,          0,   0,   0,   0,   0 }, /* PB20            */
+	/* PB19 */ { 0,          0,   0,   0,   0,   0 }, /* PB19            */
+	/* PB18 */ { 0,          0,   0,   0,   0,   0 }, /* PB18            */
+	/* PB17 */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
+	/* PB16 */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
+	/* PB15 */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
+	/* PB14 */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
+	/* PB13 */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
+	/* PB12 */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
+	/* PB11 */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
+	/* PB10 */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
+	/* PB9  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
+	/* PB8  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
+	/* PB7  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
+	/* PB6  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
+	/* PB5  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
+	/* PB4  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
+	/* PB3  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
+	/* PB2  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
+	/* PB1  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
+	/* PB0  */ { 0,          0,   0,   0,   0,   0 }  /* non-existent    */
+    },
+
+    /* Port C */
+    {   /*	      conf      ppar psor pdir podr pdat */
+	/* PC31 */ { 0,          0,   0,   0,   0,   0 }, /* PC31            */
+	/* PC30 */ { 0,          0,   0,   0,   0,   0 }, /* PC30            */
+	/* PC29 */ { 0,          0,   0,   0,   0,   0 }, /* PC29            */
+	/* PC28 */ { 0,          0,   0,   0,   0,   0 }, /* PC28            */
+	/* PC27 */ { 0,          0,   0,   0,   0,   0 }, /* PC27            */
+	/* PC26 */ { 0,          0,   0,   0,   0,   0 }, /* PC26            */
+	/* PC25 */ { 1,          1,   0,   0,   0,   0 }, /* SCC4 RxClk      */
+	/* PC24 */ { 1,          1,   0,   0,   0,   0 }, /* SCC4 TxClk      */
+	/* PC23 */ { 0,          0,   0,   0,   0,   0 }, /* PC23            */
+	/* PC22 */ { 0,          0,   0,   0,   0,   0 }, /* PC22            */
+	/* PC21 */ { 0,          0,   0,   0,   0,   0 }, /* PC21            */
+	/* PC20 */ { 0,          0,   0,   0,   0,   0 }, /* PC20            */
+	/* PC19 */ { 0,          0,   0,   0,   0,   0 }, /* PC19            */
+	/* PC18 */ { 0,          0,   0,   0,   0,   0 }, /* PC18            */
+	/* PC17 */ { 0,          0,   0,   0,   0,   0 }, /* PC17            */
+	/* PC16 */ { 0,          0,   0,   0,   0,   0 }, /* PC16            */
+	/* PC15 */ { 0,          0,   0,   0,   0,   0 }, /* PC15            */
+	/* PC14 */ { 0,          0,   0,   0,   0,   0 }, /* PC14            */
+	/* PC13 */ { 0,          0,   0,   0,   0,   0 }, /* PC13            */
+	/* PC12 */ { 0,          0,   0,   0,   0,   0 }, /* PC12            */
+	/* PC11 */ { 0,          0,   0,   0,   0,   0 }, /* PC11            */
+	/* PC10 */ { 0,          0,   0,   0,   0,   0 }, /* PC10            */
+	/* PC9  */ { 1,          1,   0,   0,   0,   0 }, /* SCC4: CTS       */
+	/* PC8  */ { 1,          1,   0,   0,   0,   0 }, /* SCC4: CD        */
+	/* PC7  */ { 0,          0,   0,   0,   0,   0 }, /* PC7             */
+	/* PC6  */ { 0,          0,   0,   0,   0,   0 }, /* PC6             */
+	/* PC5  */ { 0,          0,   0,   0,   0,   0 }, /* PC5             */
+	/* PC4  */ { 0,          0,   0,   0,   0,   0 }, /* PC4             */
+	/* PC3  */ { 0,          0,   0,   0,   0,   0 }, /* PC3             */
+	/* PC2  */ { 0,          0,   0,   0,   0,   0 }, /* PC2             */
+	/* PC1  */ { 0,          0,   0,   0,   0,   0 }, /* PC1             */
+	/* PC0  */ { 0,          0,   0,   0,   0,   0 }, /* PC0             */
+    },
+
+    /* Port D */
+    {   /*	      conf      ppar psor pdir podr pdat */
+	/* PD31 */ { 0,          0,   0,   0,   0,   0 }, /* PD31            */
+	/* PD30 */ { 0,          0,   0,   0,   0,   0 }, /* PD30            */
+	/* PD29 */ { 0,          0,   0,   0,   0,   0 }, /* PD29            */
+	/* PD28 */ { 0,          0,   0,   0,   0,   0 }, /* PD28            */
+	/* PD27 */ { 0,          0,   0,   0,   0,   0 }, /* PD27            */
+	/* PD26 */ { 0,          0,   0,   0,   0,   0 }, /* PD26            */
+	/* PD25 */ { 0,          0,   0,   0,   0,   0 }, /* PD25            */
+	/* PD24 */ { 0,          0,   0,   0,   0,   0 }, /* PD24            */
+	/* PD23 */ { 0,          0,   0,   0,   0,   0 }, /* PD23            */
+	/* PD22 */ { 1,          1,   0,   0,   0,   0 }, /* SCC4: RXD       */
+	/* PD21 */ { 1,          1,   0,   1,   0,   0 }, /* SCC4: TXD       */
+	/* PD20 */ { 1,          1,   0,   1,   0,   0 }, /* SCC4: RTS       */
+	/* PD19 */ { 0,          0,   0,   0,   0,   0 }, /* PD19            */
+	/* PD18 */ { 0,          0,   0,   0,   0,   0 }, /* PD18            */
+	/* PD17 */ { 0,          0,   0,   0,   0,   0 }, /* PD17            */
+	/* PD16 */ { 0,          0,   0,   0,   0,   0 }, /* PD16            */
+#if defined(CONFIG_HARD_I2C)
+	/* PD15 */ { 1,          1,   1,   0,   1,   0 }, /* I2C SDA         */
+	/* PD14 */ { 1,          1,   1,   0,   1,   0 }, /* I2C SCL         */
+#else
+	/* PD15 */ { 1,          0,   0,   0,   1,   1 }, /* PD15            */
+	/* PD14 */ { 1,          0,   0,   1,   1,   1 }, /* PD14            */
+#endif
+	/* PD13 */ { 0,          0,   0,   0,   0,   0 }, /* PD13            */
+	/* PD12 */ { 0,          0,   0,   0,   0,   0 }, /* PD12            */
+	/* PD11 */ { 0,          0,   0,   0,   0,   0 }, /* PD11            */
+	/* PD10 */ { 0,          0,   0,   0,   0,   0 }, /* PD10            */
+	/* PD9  */ { 0,          0,   0,   0,   0,   0 }, /* PD9             */
+	/* PD8  */ { 0,          0,   0,   0,   0,   0 }, /* PD8             */
+	/* PD7  */ { 0,          0,   0,   0,   0,   0 }, /* PD7             */
+	/* PD6  */ { 0,          0,   0,   0,   0,   0 }, /* PD6             */
+	/* PD5  */ { 0,          0,   0,   0,   0,   0 }, /* PD5             */
+	/* PD4  */ { 0,          0,   0,   0,   0,   0 }, /* PD4             */
+	/* PD3  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
+	/* PD2  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
+	/* PD1  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
+	/* PD0  */ { 0,          0,   0,   0,   0,   0 }  /* non-existent    */
+    }
+};
+
+/* Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx
+ *
+ * This routine performs standard 8260 initialization sequence
+ * and calculates the available memory size. It may be called
+ * several times to try different SDRAM configurations on both
+ * 60x and local buses.
+ */
+static long int try_init (volatile memctl8260_t * memctl, ulong sdmr,
+						  ulong orx, volatile uchar * base)
+{
+	volatile uchar c = 0xff;
+	volatile uint *sdmr_ptr;
+	volatile uint *orx_ptr;
+	ulong maxsize, size;
+	int i;
+
+	/* We must be able to test a location outsize the maximum legal size
+	 * to find out THAT we are outside; but this address still has to be
+	 * mapped by the controller. That means, that the initial mapping has
+	 * to be (at least) twice as large as the maximum expected size.
+	 */
+	maxsize = (1 + (~orx | 0x7fff))/* / 2*/;
+
+	sdmr_ptr = &memctl->memc_psdmr;
+	orx_ptr = &memctl->memc_or1;
+
+	*orx_ptr = orx;
+
+	/*
+	 * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
+	 *
+	 * "At system reset, initialization software must set up the
+	 *  programmable parameters in the memory controller banks registers
+	 *  (ORx, BRx, P/LSDMR). After all memory parameters are configured,
+	 *  system software should execute the following initialization sequence
+	 *  for each SDRAM device.
+	 *
+	 *  1. Issue a PRECHARGE-ALL-BANKS command
+	 *  2. Issue eight CBR REFRESH commands
+	 *  3. Issue a MODE-SET command to initialize the mode register
+	 *
+	 *  The initial commands are executed by setting P/LSDMR[OP] and
+	 *  accessing the SDRAM with a single-byte transaction."
+	 *
+	 * The appropriate BRx/ORx registers have already been set when we
+	 * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE.
+	 */
+
+	*sdmr_ptr = sdmr | PSDMR_OP_PREA;
+	*base = c;
+
+	*sdmr_ptr = sdmr | PSDMR_OP_CBRR;
+	for (i = 0; i < 8; i++)
+		*base = c;
+
+	*sdmr_ptr = sdmr | PSDMR_OP_MRW;
+	*(base + CONFIG_SYS_MRS_OFFS) = c;	/* setting MR on address lines */
+
+	*sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN;
+	*base = c;
+
+	size = get_ram_size ((long *)base, maxsize);
+	*orx_ptr = orx | ~(size - 1);
+
+	return (size);
+}
+
+phys_size_t initdram (int board_type)
+{
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+	volatile memctl8260_t *memctl = &immap->im_memctl;
+
+	long psize;
+
+	memctl->memc_psrt = CONFIG_SYS_PSRT;
+	memctl->memc_mptpr = CONFIG_SYS_MPTPR;
+
+#ifndef CONFIG_SYS_RAMBOOT
+	/* 60x SDRAM setup:
+	 */
+	psize = try_init (memctl, CONFIG_SYS_PSDMR, CONFIG_SYS_OR1,
+						  (uchar *) CONFIG_SYS_SDRAM_BASE);
+#endif /* CONFIG_SYS_RAMBOOT */
+
+	icache_enable ();
+
+	return (psize);
+}
+
+int checkboard(void)
+{
+	puts ("Board: mgcoge\n");
+
+	return 0;
+}
+
+/*
+ * Early board initalization.
+ */
+int board_early_init_r (void)
+{
+	/* setup the UPIOx */
+	out_8((u8 *)(CONFIG_SYS_PIGGY_BASE + 0x02), 0xc0);
+	out_8((u8 *)(CONFIG_SYS_PIGGY_BASE + 0x03), 0x15);
+	return 0;
+}
+
+int hush_init_var (void)
+{
+	ivm_read_eeprom ();
+	return 0;
+}
+
+#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
+extern int fdt_set_node_and_value (void *blob,
+                                char *nodename,
+                                char *regname,
+                                void *var,
+                                int size);
+
+/*
+ * update "memory" property in the blob
+ */
+void ft_blob_update (void *blob, bd_t *bd)
+{
+	ulong memory_data[2] = {0};
+	ulong flash_data[8] = {0};
+
+	memory_data[0] = cpu_to_be32 (bd->bi_memstart);
+	memory_data[1] = cpu_to_be32 (bd->bi_memsize);
+	fdt_set_node_and_value (blob, "/memory", "reg", memory_data,
+				sizeof (memory_data));
+
+	/* update Flash addr, size */
+	flash_data[2] = cpu_to_be32 (CONFIG_SYS_FLASH_BASE);
+	flash_data[3] = cpu_to_be32 (CONFIG_SYS_FLASH_SIZE);
+	flash_data[4] = cpu_to_be32 (5);
+	flash_data[5] = cpu_to_be32 (0);
+	flash_data[6] = cpu_to_be32 (CONFIG_SYS_FLASH_BASE_1);
+	flash_data[7] = cpu_to_be32 (CONFIG_SYS_FLASH_SIZE_1);
+	fdt_set_node_and_value (blob, "/localbus", "ranges", flash_data,
+				sizeof (flash_data));
+	/* MAC addr */
+	fdt_set_node_and_value (blob, "/soc/cpm/ethernet", "mac-address",
+				bd->bi_enetaddr, sizeof (u8) * 6);
+}
+
+void ft_board_setup (void *blob, bd_t *bd)
+{
+	ft_cpu_setup (blob, bd);
+	ft_blob_update (blob, bd);
+}
+#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */
diff --git a/board/keymile/mgsuvd/Makefile b/board/keymile/mgsuvd/Makefile
new file mode 100644
index 0000000..b2145f9
--- /dev/null
+++ b/board/keymile/mgsuvd/Makefile
@@ -0,0 +1,47 @@
+#
+# (C) Copyright 2007
+# Heiko Schocher, DENX Software Engineering, hs@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../common)
+endif
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS	= $(BOARD).o ../common/common.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/keymile/mgsuvd/config.mk b/board/keymile/mgsuvd/config.mk
new file mode 100644
index 0000000..8625cea
--- /dev/null
+++ b/board/keymile/mgsuvd/config.mk
@@ -0,0 +1,28 @@
+#
+# (C) Copyright 2007
+# Heiko Schocher, DENX Software Engineering, hs@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# mgsvud boards
+#
+
+TEXT_BASE = 0xf0000000
diff --git a/board/keymile/mgsuvd/mgsuvd.c b/board/keymile/mgsuvd/mgsuvd.c
new file mode 100644
index 0000000..0fd28da
--- /dev/null
+++ b/board/keymile/mgsuvd/mgsuvd.c
@@ -0,0 +1,204 @@
+/*
+ * (C) Copyright 2007
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <mpc8xx.h>
+#include <asm/io.h>
+
+#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
+#include <libfdt.h>
+#endif
+
+extern int ivm_read_eeprom (void);
+
+DECLARE_GLOBAL_DATA_PTR;
+
+const uint sdram_table[] =
+{
+	0x0f07fc04, 0x0ffffc04, 0x00bdfc04, 0x0ff77c00,
+	0x1ffffc05, 0xfffffc04, 0xfffffc04, 0xfffffc04,
+	/* 0x08 Burst Read */
+	0x0f07fc04, 0x0ffffc04, 0x00bdfc04, 0x00fffc00,
+	0x00fffc00, 0x00fffc00, 0x0ff77c00, 0x1ffffc05,
+	/* 0x10 Load mode register */
+	0x0ffffc34, 0x0ff57c04, 0x0ffffc04, 0x1ffffc05,
+	0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
+	/* 0x18 Single Write */
+	0x0f07fc04, 0x0ffffc00, 0x00bd7c04, 0x0ffffc04,
+	0x0ff77c04, 0x1ffffc05, 0xfffffc04, 0xfffffc04,
+	/* 0x20 Burst Write */
+	0x0f07fc04, 0x0ffffc00, 0x00bd7c00, 0x00fffc00,
+	0x00fffc00, 0x00fffc04, 0x0ffffc04, 0x0ff77c04,
+	0x1ffffc05, 0xfffffc04, 0xfffffc04, 0xfffffc04,
+	0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
+	/* 0x30 Precharge all and Refresh */
+	0x0ff77c04, 0x0ffffc04, 0x0ff5fc84, 0x0ffffc04,
+	0x0ffffc04, 0x0ffffc84, 0x1ffffc05, 0xfffffc04,
+	0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
+	/* 0x3C Exception */
+	0x7ffffc04, 0xfffffc07, 0xfffffc04, 0xfffffc04,
+};
+
+int checkboard (void)
+{
+	puts ("Board: Keymile mgsuvd\n");
+	return (0);
+}
+
+phys_size_t initdram (int board_type)
+{
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	long int size;
+
+	upmconfig (UPMB, (uint *) sdram_table,
+			   sizeof (sdram_table) / sizeof (uint));
+
+	/*
+	 * Preliminary prescaler for refresh (depends on number of
+	 * banks): This value is selected for four cycles every 62.4 us
+	 * with two SDRAM banks or four cycles every 31.2 us with one
+	 * bank. It will be adjusted after memory sizing.
+	 */
+	memctl->memc_mptpr = CONFIG_SYS_MPTPR;
+
+	/*
+	 * The following value is used as an address (i.e. opcode) for
+	 * the LOAD MODE REGISTER COMMAND during SDRAM initialisation. If
+	 * the port size is 32bit the SDRAM does NOT "see" the lower two
+	 * address lines, i.e. mar=0x00000088 -> opcode=0x00000022 for
+	 * MICRON SDRAMs:
+	 * ->    0 00 010 0 010
+	 *       |  |   | |   +- Burst Length = 4
+	 *       |  |   | +----- Burst Type   = Sequential
+	 *       |  |   +------- CAS Latency  = 2
+	 *       |  +----------- Operating Mode = Standard
+	 *       +-------------- Write Burst Mode = Programmed Burst Length
+	 */
+	memctl->memc_mar = CONFIG_SYS_MAR;
+
+	/*
+	 * Map controller banks 1 to the SDRAM banks 1 at
+	 * preliminary addresses - these have to be modified after the
+	 * SDRAM size has been determined.
+	 */
+	memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM;
+	memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM;
+
+	memctl->memc_mbmr = CONFIG_SYS_MBMR & (~(MBMR_PTBE));	/* no refresh yet */
+
+	udelay (200);
+
+	/* perform SDRAM initializsation sequence */
+
+	memctl->memc_mcr = 0x80802830;	/* SDRAM bank 0 */
+	udelay (1);
+	memctl->memc_mcr = 0x80802110;	/* SDRAM bank 0 - execute twice */
+	udelay (1);
+
+	memctl->memc_mbmr |= MBMR_PTBE;	/* enable refresh */
+
+	udelay (1000);
+
+	/*
+	 * Check Bank 0 Memory Size for re-configuration
+	 *
+	 */
+	size =  get_ram_size(SDRAM_BASE1_PRELIM, SDRAM_MAX_SIZE);
+
+	udelay (1000);
+
+	debug ("SDRAM Bank 0: %ld MB\n", size >> 20);
+
+	return (size);
+}
+
+/*
+ * Early board initalization.
+ */
+int board_early_init_r(void)
+{
+	/* setup the UPIOx */
+	out_8((u8 *)(CONFIG_SYS_PIGGY_BASE + 0x02), 0xc0);
+	out_8((u8 *)(CONFIG_SYS_PIGGY_BASE + 0x03), 0x35);
+	return 0;
+}
+
+int hush_init_var (void)
+{
+	ivm_read_eeprom ();
+	return 0;
+}
+
+#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
+extern int fdt_set_node_and_value (void *blob,
+                                char *nodename,
+                                char *regname,
+                                void *var,
+                                int size);
+
+/*
+ * update "memory" property in the blob
+ */
+void ft_blob_update (void *blob, bd_t *bd)
+{
+	ulong brg_data[1] = {0};
+	ulong memory_data[2] = {0};
+	ulong flash_data[4] = {0};
+
+	memory_data[0] = cpu_to_be32 (bd->bi_memstart);
+	memory_data[1] = cpu_to_be32 (bd->bi_memsize);
+	fdt_set_node_and_value (blob, "/memory", "reg", memory_data,
+				sizeof (memory_data));
+
+	flash_data[2] = cpu_to_be32 (bd->bi_flashstart);
+	flash_data[3] = cpu_to_be32 (bd->bi_flashsize);
+	fdt_set_node_and_value (blob, "/localbus", "ranges", flash_data,
+				sizeof (flash_data));
+
+	/* BRG */
+	brg_data[0] = cpu_to_be32 (bd->bi_busfreq);
+	fdt_set_node_and_value (blob, "/soc/cpm", "brg-frequency", brg_data,
+				sizeof (brg_data));
+
+	/* MAC adr */
+	fdt_set_node_and_value (blob, "/soc/cpm/ethernet", "mac-address",
+				bd->bi_enetaddr, sizeof (u8) * 6);
+}
+
+void ft_board_setup(void *blob, bd_t *bd)
+{
+	ft_cpu_setup (blob, bd);
+	ft_blob_update (blob, bd);
+}
+#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */
+
+int i2c_soft_read_pin (void)
+{
+	int val;
+
+	*(unsigned short *)(I2C_BASE_DIR) &=  ~SDA_CONF;
+	udelay(1);
+	val = *(unsigned char *)(I2C_BASE_PORT);
+
+	return ((val & SDA_BIT) == SDA_BIT);
+}
diff --git a/board/keymile/mgsuvd/u-boot.lds b/board/keymile/mgsuvd/u-boot.lds
new file mode 100644
index 0000000..26aa5d6
--- /dev/null
+++ b/board/keymile/mgsuvd/u-boot.lds
@@ -0,0 +1,143 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)	}
+  .rela.text     : { *(.rela.text)	}
+  .rel.data      : { *(.rel.data)	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
+  .rel.got       : { *(.rel.got)	}
+  .rela.got      : { *(.rela.got)	}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)	}
+  .rela.bss      : { *(.rela.bss)	}
+  .rel.plt       : { *(.rel.plt)	}
+  .rela.plt      : { *(.rela.plt)	}
+  .init          : { *(.init)		}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/mpc8xx/start.o		(.text)
+    cpu/mpc8xx/traps.o		(.text)
+    common/dlmalloc.o		(.text)
+    lib_ppc/ppcstring.o		(.text)
+    lib_generic/vsprintf.o	(.text)
+    lib_generic/crc32.o		(.text)
+    lib_generic/zlib.o		(.text)
+    lib_ppc/cache.o		(.text)
+    lib_ppc/time.o		(.text)
+
+    . = DEFINED(env_offset) ? env_offset : .;
+    common/env_embedded.o	(.ppcenv)
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss (NOLOAD)       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}