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authorValentin Longchamp <valentin.longchamp@keymile.com>2012-07-05 05:05:09 +0000
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>2012-07-07 14:07:37 +0200
commitdbdee4ca591a3bf19446d8ab89285835e210b378 (patch)
tree90be6f7295739d2edb4524cd68fa0516ff6a2bf2 /board/keymile
parentbcac5b1b2c4f5f44a512dee7b0ac9ed64fd0bed0 (diff)
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arm/km: support the 2 PCIe fpga resets
The PCIe FPGAs now have to support 2 resets: one for the non traffic affecting part (PCIe) and one for the traffic affecting part. When the FPGA is not reconfigured, we only reset the PCIe part. Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
Diffstat (limited to 'board/keymile')
-rw-r--r--board/keymile/km_arm/fpga_config.c13
1 files changed, 9 insertions, 4 deletions
diff --git a/board/keymile/km_arm/fpga_config.c b/board/keymile/km_arm/fpga_config.c
index 8ac6393..fcc5fe6 100644
--- a/board/keymile/km_arm/fpga_config.c
+++ b/board/keymile/km_arm/fpga_config.c
@@ -99,7 +99,7 @@ static int boco_set_bits(u8 reg, u8 flags)
#define FPGA_INIT_B 0x10
#define FPGA_DONE 0x20
-static int fpga_done()
+static int fpga_done(void)
{
int ret = 0;
u8 regval;
@@ -206,25 +206,30 @@ int wait_for_fpga_config(void)
}
#define PRST1 0x4
-#define BRIDGE_RST 0x4
+#define PCIE_RST 0x10
+#define TRAFFIC_RST 0x04
int fpga_reset(void)
{
int ret = 0;
+ u8 resets;
if (!check_boco2()) {
/* we do not have BOCO2, this is not really used */
return 0;
}
- ret = boco_clear_bits(PRST1, BRIDGE_RST);
+ /* if we have skipped, we only want to reset the PCIe part */
+ resets = skip ? PCIE_RST : PCIE_RST | TRAFFIC_RST;
+
+ ret = boco_clear_bits(PRST1, resets);
if (ret)
return ret;
/* small delay for the pulse */
udelay(10);
- ret = boco_set_bits(PRST1, BRIDGE_RST);
+ ret = boco_set_bits(PRST1, resets);
if (ret)
return ret;