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| author | Heiko Schocher <hs@denx.de> | 2009-02-24 11:30:40 +0100 |
|---|---|---|
| committer | Kim Phillips <kim.phillips@freescale.com> | 2009-03-05 18:21:17 -0600 |
| commit | 118cbe3c35c898f8d020b29d6dc180307cacf147 (patch) | |
| tree | de83a279e267143ec117b5c96c4b7e9a24dac6a2 /board/keymile/kmeter1 | |
| parent | c1bce4fff750d734b1fa7467eb08f93902c97ca6 (diff) | |
| download | u-boot-imx-118cbe3c35c898f8d020b29d6dc180307cacf147.zip u-boot-imx-118cbe3c35c898f8d020b29d6dc180307cacf147.tar.gz u-boot-imx-118cbe3c35c898f8d020b29d6dc180307cacf147.tar.bz2 | |
83xx, kmeter1: autodetect size of DDR II RAM
it is possible that some board variants have different DDR II
RAM sizes. So we autodetect the size of the assembled RAM.
Signed-off-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Diffstat (limited to 'board/keymile/kmeter1')
| -rw-r--r-- | board/keymile/kmeter1/kmeter1.c | 28 |
1 files changed, 18 insertions, 10 deletions
diff --git a/board/keymile/kmeter1/kmeter1.c b/board/keymile/kmeter1/kmeter1.c index a3c58ae..4f41f1d 100644 --- a/board/keymile/kmeter1/kmeter1.c +++ b/board/keymile/kmeter1/kmeter1.c @@ -29,6 +29,8 @@ #include "../common/common.h" +extern void disable_addr_trans (void); +extern void enable_addr_trans (void); const qe_iop_conf_t qe_iop_conf_tab[] = { /* port pin dir open_drain assign */ @@ -111,16 +113,7 @@ int fixed_sdram(void) u32 ddr_size; u32 ddr_size_log2; - msize = CONFIG_SYS_DDR_SIZE; - for (ddr_size = msize << 20, ddr_size_log2 = 0; - (ddr_size > 1); ddr_size = ddr_size >> 1, ddr_size_log2++) { - if (ddr_size & 1) - return -1; - } - - im->sysconf.ddrlaw[0].ar = - LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE); - + im->sysconf.ddrlaw[0].ar = LAWAR_EN | 0x1e; im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS; im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG; im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; @@ -136,6 +129,21 @@ int fixed_sdram(void) udelay (200); im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN; + msize = CONFIG_SYS_DDR_SIZE << 20; + disable_addr_trans (); + msize = get_ram_size (CONFIG_SYS_DDR_BASE, msize); + enable_addr_trans (); + msize /= (1024 * 1024); + if (CONFIG_SYS_DDR_SIZE != msize) { + for (ddr_size = msize << 20, ddr_size_log2 = 0; + (ddr_size > 1); ddr_size = ddr_size >> 1, ddr_size_log2++) + if (ddr_size & 1) + return -1; + im->sysconf.ddrlaw[0].ar = + LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE); + im->ddr.csbnds[0].csbnds = (((msize / 16) - 1) & 0xff); + } + return msize; } |