powerpc: 83xx: add support for the kmeter1 board

This patch adds support for the kmeter1 board from Keymile,
based on a Freescale MPC8360 CPU.

- serial console on UART 1
- 256 MB DDR2 RAM
- 64 MB NOR Flash
- Ethernet RMII Mode over UCC4
- PHY SMSC LAN8700

Signed-off-by: Heiko Schocher <hs@denx.de>

1 files changed, 153 insertions, 0 deletions

diff --git a/board/keymile/kmeter1/kmeter1.c b/board/keymile/kmeter1/kmeter1.c
new file mode 100644
index 0000000..f9a59a64
--- /dev/null
+++ b/board/keymile/kmeter1/kmeter1.c
@@ -0,0 +1,153 @@
+/*
+ * Copyright (C) 2006 Freescale Semiconductor, Inc.
+ *                    Dave Liu <daveliu@freescale.com>
+ *
+ * Copyright (C) 2007 Logic Product Development, Inc.
+ *                    Peter Barada <peterb@logicpd.com>
+ *
+ * Copyright (C) 2007 MontaVista Software, Inc.
+ *                    Anton Vorontsov <avorontsov@ru.mvista.com>
+ *
+ * (C) Copyright 2008
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+#include <common.h>
+#include <ioports.h>
+#include <mpc83xx.h>
+#include <i2c.h>
+#include <miiphy.h>
+#include <asm/io.h>
+#include <asm/mmu.h>
+#include <pci.h>
+#include <libfdt.h>
+
+const qe_iop_conf_t qe_iop_conf_tab[] = {
+	/* port pin dir open_drain assign */
+
+	/* MDIO */
+	{0,  1, 3, 0, 2}, /* MDIO */
+	{0,  2, 1, 0, 1}, /* MDC */
+
+	/* UCC4 - UEC */
+	{1, 14, 1, 0, 1}, /* TxD0 */
+	{1, 15, 1, 0, 1}, /* TxD1 */
+	{1, 20, 2, 0, 1}, /* RxD0 */
+	{1, 21, 2, 0, 1}, /* RxD1 */
+	{1, 18, 1, 0, 1}, /* TX_EN */
+	{1, 26, 2, 0, 1}, /* RX_DV */
+	{1, 27, 2, 0, 1}, /* RX_ER */
+	{1, 24, 2, 0, 1}, /* COL */
+	{1, 25, 2, 0, 1}, /* CRS */
+	{2, 15, 2, 0, 1}, /* TX_CLK - CLK16 */
+	{2, 16, 2, 0, 1}, /* RX_CLK - CLK17 */
+
+	/* DUART - UART2 */
+	{5,  0, 1, 0, 2}, /* UART2_SOUT */
+	{5,  2, 1, 0, 1}, /* UART2_RTS */
+	{5,  3, 2, 0, 2}, /* UART2_SIN */
+	{5,  1, 2, 0, 3}, /* UART2_CTS */
+
+	/* END of table */
+	{0,  0, 0, 0, QE_IOP_TAB_END},
+};
+
+int board_early_init_r (void)
+{
+	void *reg = (void *)(CONFIG_SYS_IMMR + 0x14a8);
+	u32 val;
+
+	/*
+	 * Because of errata in the UCCs, we have to write to the reserved
+	 * registers to slow the clocks down.
+	 */
+	val = in_be32 (reg);
+	/* UCC1 */
+	val |= 0x00003000;
+	/* UCC2 */
+	val |= 0x0c000000;
+	out_be32 (reg, val);
+	/* enable the PHY on the PIGGY */
+	setbits (8, (void *)(CONFIG_SYS_PIGGY_BASE + 0x10003), 0x01);
+
+	return 0;
+}
+
+int fixed_sdram(void)
+{
+	volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
+	u32 msize = 0;
+	u32 ddr_size;
+	u32 ddr_size_log2;
+
+	msize = CONFIG_SYS_DDR_SIZE;
+	for (ddr_size = msize << 20, ddr_size_log2 = 0;
+	     (ddr_size > 1); ddr_size = ddr_size >> 1, ddr_size_log2++) {
+		if (ddr_size & 1)
+			return -1;
+	}
+
+	im->sysconf.ddrlaw[0].ar =
+	    LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
+
+	im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS;
+	im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
+	im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
+	im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
+	im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
+	im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
+	im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
+	im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
+	im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
+	im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
+	im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
+	im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;
+	udelay (200);
+	im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
+
+	return msize;
+}
+
+phys_size_t initdram (int board_type)
+{
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC)
+	extern void ddr_enable_ecc (unsigned int dram_size);
+#endif
+	volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
+	u32 msize = 0;
+
+	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
+		return -1;
+
+	/* DDR SDRAM - Main SODIMM */
+	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
+	msize = fixed_sdram ();
+
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC)
+	/*
+	 * Initialize DDR ECC byte
+	 */
+	ddr_enable_ecc (msize * 1024 * 1024);
+#endif
+
+	/* return total bus SDRAM size(bytes)  -- DDR */
+	return (msize * 1024 * 1024);
+}
+
+int checkboard (void)
+{
+	puts ("Board: Keymile kmeter1\n");
+	return 0;
+}
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+void ft_board_setup (void *blob, bd_t *bd)
+{
+	ft_cpu_setup (blob, bd);
+}
+#endif