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| author | Valentin Longchamp <valentin.longchamp@keymile.com> | 2011-06-16 18:11:15 +0530 |
|---|---|---|
| committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2011-07-04 10:55:28 +0200 |
| commit | 01fa4e8cded8c3c610b0ea10ad817a7ca8c72517 (patch) | |
| tree | 5dc3036d1208aacc6af02e67c0b8e35dd26fa746 /board/keymile/km_arm | |
| parent | 83b40c31466a2c0113686806767af7e163e69d1a (diff) | |
| download | u-boot-imx-01fa4e8cded8c3c610b0ea10ad817a7ca8c72517.zip u-boot-imx-01fa4e8cded8c3c610b0ea10ad817a7ca8c72517.tar.gz u-boot-imx-01fa4e8cded8c3c610b0ea10ad817a7ca8c72517.tar.bz2 | |
arm/km: add support for portl2 board
This adds support for the keymile Kirkwood BEC portl2 board. This board
relies on the km_arm (km_kirkwood) BEC.
The egiga driver is configured for a 100M full-duplex, A/N off connnection
to the backplane. This board has always ethernet present, because it is
connected to the marvell switch similar to mgcoge3un. The reset_phy
functionality is also the same to mgcoge3un.
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
cc: Prafulla Wadaskar <prafulla@marvell.com>
cc: Heiko Schocher <hs@denx.de>
Diffstat (limited to 'board/keymile/km_arm')
| -rw-r--r-- | board/keymile/km_arm/km_arm.c | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/board/keymile/km_arm/km_arm.c b/board/keymile/km_arm/km_arm.c index ed6ede3..5da856f 100644 --- a/board/keymile/km_arm/km_arm.c +++ b/board/keymile/km_arm/km_arm.c @@ -130,10 +130,12 @@ int startup_allowed(void) return 1; return 0; } +#endif +#if (defined(CONFIG_MGCOGE3UN)|defined(CONFIG_PORTL2)) /* - * mgcoge3un has always ethernet present. Its connected to the 6061 switch - * and provides ICNev and piggy4 connections. + * These two boards have always ethernet present. Its connected to the mv + * switch. */ int ethernet_present(void) { @@ -335,7 +337,7 @@ void dram_init_banksize(void) } } -#if defined(CONFIG_MGCOGE3UN) +#if (defined(CONFIG_MGCOGE3UN)|defined(CONFIG_PORTL2)) #define PHY_LED_SEL 0x18 #define PHY_LED0_LINK (0x5) |