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| author | Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> | 2008-10-16 15:01:15 +0200 |
|---|---|---|
| committer | Wolfgang Denk <wd@denx.de> | 2008-10-18 21:54:03 +0200 |
| commit | 6d0f6bcf337c5261c08fabe12982178c2c489d76 (patch) | |
| tree | ae13958ffa9c6b58c2ea97aac07a4ad2f04a350f /board/jse/jse.c | |
| parent | 71edc271816ec82cf0550dd6980be2da3cc2ad9e (diff) | |
| download | u-boot-imx-6d0f6bcf337c5261c08fabe12982178c2c489d76.zip u-boot-imx-6d0f6bcf337c5261c08fabe12982178c2c489d76.tar.gz u-boot-imx-6d0f6bcf337c5261c08fabe12982178c2c489d76.tar.bz2 | |
rename CFG_ macros to CONFIG_SYS
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Diffstat (limited to 'board/jse/jse.c')
| -rw-r--r-- | board/jse/jse.c | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/board/jse/jse.c b/board/jse/jse.c index 9290814..6a6b9dd 100644 --- a/board/jse/jse.c +++ b/board/jse/jse.c @@ -67,7 +67,7 @@ int board_early_init_f (void) /* EBC0_B1CR: BAS=x, BS=0(1MB), BU=3(R/W), BW=0(8bits) */ mtdcr (ebccfga, pb1cr); - mtdcr (ebccfgd, CFG_SYSTEMACE_BASE | 0x00018000); + mtdcr (ebccfgd, CONFIG_SYS_SYSTEMACE_BASE | 0x00018000); /* Enable the /PerWE output as /PerWE, instead of /PCIINT. */ /* CPC0_CR1 |= PCIPW */ @@ -95,11 +95,11 @@ int checkboard (void) /* check that the SystemACE chip is alive. */ printf ("ACE: "); - vers = readw (CFG_SYSTEMACE_BASE + 0x16); + vers = readw (CONFIG_SYS_SYSTEMACE_BASE + 0x16); printf ("SystemACE %u.%u (build %u)", (vers >> 12) & 0x0f, (vers >> 8) & 0x0f, vers & 0xff); - status = readl (CFG_SYSTEMACE_BASE + 0x04); + status = readl (CONFIG_SYS_SYSTEMACE_BASE + 0x04); #ifdef DEBUG printf (" STATUS=0x%08x", status); #endif @@ -110,23 +110,23 @@ int checkboard (void) if (status & 0x04) { /* CONTROLREG = CFGPROG */ - writew (0x1000, CFG_SYSTEMACE_BASE + 0x18); + writew (0x1000, CONFIG_SYS_SYSTEMACE_BASE + 0x18); udelay (500); /* CONTROLREG = CFGRESET */ - writew (0x0080, CFG_SYSTEMACE_BASE + 0x18); + writew (0x0080, CONFIG_SYS_SYSTEMACE_BASE + 0x18); udelay (500); - writew (0x0000, CFG_SYSTEMACE_BASE + 0x18); + writew (0x0000, CONFIG_SYS_SYSTEMACE_BASE + 0x18); /* CONTROLREG = CFGSTART */ - writew (0x0020, CFG_SYSTEMACE_BASE + 0x18); + writew (0x0020, CONFIG_SYS_SYSTEMACE_BASE + 0x18); - status = readl (CFG_SYSTEMACE_BASE + 0x04); + status = readl (CONFIG_SYS_SYSTEMACE_BASE + 0x04); } } /* Wait for the SystemACE to program its chain of devices. */ while ((status & 0x84) == 0x00) { udelay (500); - status = readl (CFG_SYSTEMACE_BASE + 0x04); + status = readl (CONFIG_SYS_SYSTEMACE_BASE + 0x04); } if (status & 0x04) |