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authorAnthony Felice <tony.felice@timesys.com>2014-09-06 19:47:06 +0200
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>2014-10-07 13:08:31 +0200
commitc19a8bc5711ec63e905ef91f045a1489f0aa3cb0 (patch)
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parent1454ba8e56d88a8b95ac8050cde2c07c651cd0ae (diff)
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vf610twr: Tune DDR initialization settings
Removed settings in unsupported register fields. They didn’t do anything, and in most cases, were not documented in the reference manual. Changed register settings to comply with JEDEC required values. Changed timing parameters because they included full clock periods that were doing nothing. Signed-off-by: Anthony Felice <tony.felice@timesys.com> [rebased on v2014.10-rc2] Signed-off-by: Stefan Agner <stefan@agner.ch>
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