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authorLokesh Vutla <lokeshvutla@ti.com>2013-03-27 20:24:42 +0000
committerTom Rini <trini@ti.com>2013-05-10 08:25:55 -0400
commit166e5cc6278881f2951e7c06a122ecb080dc8968 (patch)
tree4df87ca079c9eaae1600430eafde995d2b087476 /board/isee
parent8ce4e5f9329183a162775946558092166cb7cab3 (diff)
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arm: omap: emif: Fix DDR3 init after warm reset
EMIF supports a global warm reset mode, during which the EMIF keeps the SDRAM content. But if leveling is enabled at the time of warm reset for DDR3, the following steps needs to be done after warm reset: 1) Keep EMIF in self refresh mode. 2) Reset PHY to bring back the PHY to a known state. 3) Start Levelling procedure. Doing the same. And also enabling DLL lock and code output after warm reset. Tested on OMAP5432 ES2.0 Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
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