summaryrefslogtreecommitdiff
path: root/board/isee
diff options
context:
space:
mode:
authorHeiko Schocher <hs@denx.de>2013-07-30 10:48:54 +0530
committerTom Rini <trini@ti.com>2013-08-15 08:51:10 -0400
commit0660481a59cccd324fc2dfcad9734318a8c25a90 (patch)
treeebebc64d145f50a26cf1cba98ba3e8ce4c3b9811 /board/isee
parent95cb69faeb45f6396a1336bff201a50ea1677d85 (diff)
downloadu-boot-imx-0660481a59cccd324fc2dfcad9734318a8c25a90.zip
u-boot-imx-0660481a59cccd324fc2dfcad9734318a8c25a90.tar.gz
u-boot-imx-0660481a59cccd324fc2dfcad9734318a8c25a90.tar.bz2
ARM: AM33xx: Move s_init to a common place
s_init has the same outline for all the AM33xx based board. So making it generic. This also helps in addition of new Soc with minimal changes. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Heiko Schocher <hs@denx.de> Signed-off-by: Tom Rini <trini@ti.com> Tested-by: Heiko Schocher <hs@denx.de> Acked-by: Heiko Schocher <hs@denx.de>
Diffstat (limited to 'board/isee')
-rw-r--r--board/isee/igep0033/board.c50
1 files changed, 8 insertions, 42 deletions
diff --git a/board/isee/igep0033/board.c b/board/isee/igep0033/board.c
index a065a74..f71aaa0 100644
--- a/board/isee/igep0033/board.c
+++ b/board/isee/igep0033/board.c
@@ -27,8 +27,6 @@
DECLARE_GLOBAL_DATA_PTR;
-static struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
-
/* MII mode defines */
#define RMII_MODE_ENABLE 0x4D
@@ -76,54 +74,22 @@ const struct dpll_params *get_dpll_ddr_params(void)
return &dpll_ddr;
}
-#endif
-
-/*
- * Early system init of muxing and clocks.
- */
-void s_init(void)
+void set_uart_mux_conf(void)
{
- /*
- * Save the boot parameters passed from romcode.
- * We cannot delay the saving further than this,
- * to prevent overwrites.
- */
-#ifdef CONFIG_SPL_BUILD
- save_omap_boot_params();
-#endif
-
- /* WDT1 is already running when the bootloader gets control
- * Disable it to avoid "random" resets
- */
- writel(0xAAAA, &wdtimer->wdtwspr);
- while (readl(&wdtimer->wdtwwps) != 0x0)
- ;
- writel(0x5555, &wdtimer->wdtwspr);
- while (readl(&wdtimer->wdtwwps) != 0x0)
- ;
-
-#ifdef CONFIG_SPL_BUILD
- setup_clocks_for_console();
-
enable_uart0_pin_mux();
+}
- uart_soft_reset();
- gd = &gdata;
-
- preloader_console_init();
-
- prcm_init();
-
- /* Enable RTC32K clock */
- rtc32k_enable();
-
- /* Configure board pin mux */
+void set_mux_conf_regs(void)
+{
enable_board_pin_mux();
+}
+void sdram_init(void)
+{
config_ddr(303, K4B2G1646EBIH9_IOCTRL_VALUE, &ddr3_data,
&ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
-#endif
}
+#endif
/*
* Basic board specific setup. Pinmux has been handled already.