IGEP0046: SPL and UBOOT Testisee_imx_v2017.03_4.9.11_1.0.0_ga_TEST

it was created the following source files in board/isee/common: igep_test.c and igep_test.h
it was CLEARED igep board folders that do not belong to u-boot-imx like igep00x0 and igep0030

Signed-off-by: Jose Miguel Sanchez Sanabria <jsanabria@iseebcn.com>

9 files changed, 839 insertions, 508 deletions

diff --git a/board/isee/igep0046/MAINTAINERS b/board/isee/igep0046/MAINTAINERS
index aefd87b..be4801b 100644
--- a/board/isee/igep0046/MAINTAINERS
+++ b/board/isee/igep0046/MAINTAINERS
@@ -3,4 +3,4 @@ M:	Jose Miguel Sanchez Sanabria <jsanabria@iseebcn.com>
 S:	Maintained
 F:	board/isee/igep0046/igep0046.c
 F:	include/configs/igep0046.h
-F:	configs/mx6dl_igep0046_2G_defconfig
+F:	configs/mx6dl_igep0046_2G_defconfig
\ No newline at end of file
diff --git a/board/isee/igep0046/Makefile b/board/isee/igep0046/Makefile
index 6e521c9..b7d5f16 100644
--- a/board/isee/igep0046/Makefile
+++ b/board/isee/igep0046/Makefile
@@ -1,11 +1,12 @@
 #
-# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+# Copyright (C) 2016 ISEE 2007 SL - http://www.isee.biz
 #
-# (C) Copyright 2011 Freescale Semiconductor, Inc.
+# Source file for IGEP0046 board
+#
+# Author: Jose Miguel Sanchez Sanabria <jsanabria@iseebcn.com>
 #
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-obj-y  += igep0046_eeprom.o
 obj-$(CONFIG_POWER_PFUZE100)	+= pfuze.o
 obj-y  += igep0046.o
diff --git a/board/isee/igep0046/igep0046.c b/board/isee/igep0046/igep0046.c
index cdc0466..d3877d8 100644
--- a/board/isee/igep0046/igep0046.c
+++ b/board/isee/igep0046/igep0046.c
@@ -32,10 +32,12 @@
 #include <power/pmic.h>
 #include <power/pfuze100_pmic.h>
 #include "pfuze.h"
-#include "igep0046_eeprom.h"
 #include "../common/igep_common.h"
+#include "../common/igep_eeprom.h"
+#include "../common/igep_test.h"
 #include <usb.h>
 #include <mmc.h>
+#include <net.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -92,6 +94,9 @@ DECLARE_GLOBAL_DATA_PTR;
 #define GPIO_LED_RED2		IMX_GPIO_NR(4, 20)
 #define GPIO_LED_GREEN2		IMX_GPIO_NR(4, 17)
 
+/* Define Revision */
+#define TEST_REVISION 4
+
 int dram_init(void)
 {
 	gd->ram_size = imx_ddr_size();
@@ -187,11 +192,12 @@ static iomux_v3_cfg_t const init_pads[] =
 	MX6_PAD_CSI0_DAT7__GPIO5_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL),
 	#endif
 };
-#define STATION 0x01
-const uchar igep_mac0 [6] = { 0x02, 0xBA, 0xD0, 0xBA, 0xD0, STATION };
+#define STATION 0x02
+const uchar igep_mac0 [6] = { 0x02, 0xBA, 0xD0, 0xBB, 0xD1, STATION };
 uchar enetaddr[6];	
 static int igep_eeprom_valid = 0;
 static struct igep_mf_setup igep0046_eeprom_config;
+static int net_fail = 0;
 
 /* I2C MUX */
 #ifdef CONFIG_SYS_I2C
@@ -406,7 +412,9 @@ int board_eth_init(bd_t *bis)
 	get_mac_address();
 	setup_iomux_enet();
 #ifdef CONFIG_FEC_MXC
-	cpu_eth_init(bis);
+	if(cpu_eth_init(bis)){
+		net_fail = 1;
+	}
 #endif
 	return 0;
 }
@@ -421,19 +429,265 @@ int board_early_init_f(void)
 	setup_iomux_uart();
 
 	imx_iomux_v3_setup_multiple_pads(init_pads, ARRAY_SIZE(init_pads));
+	return 0;
+}
 
-	/* configure LEDS - SPL = 1 YELLOW */
-	gpio_direction_output(GPIO_LED_RED1, 1);
-	gpio_direction_output(GPIO_LED_GREEN1, 1);
+/* ------------- HERE IT WILL GO THE TEST FUNCTIONS THAT ITS EASIER TO BE HERE ------------- */
+
+void error_loop(int casee){
+
+	int su = 1;
+	/* Turn off LEDs */
+	gpio_direction_output(GPIO_LED_RED1, 0);
+	gpio_direction_output(GPIO_LED_GREEN1, 0);
 	gpio_direction_output(GPIO_LED_RED2, 0);
 	gpio_direction_output(GPIO_LED_GREEN2, 0);
+
+	switch (casee){
+		case 0:
+			/* I2C BUS ERROR */
+			/* Turn on LED combination to notify I2C FAILED */
+			/* We will infinite loop here 1 every 1 sec, combination is red-green switching every sec */
+			while(1){
+				if (su){
+					gpio_direction_output(GPIO_LED_RED1, 1);
+					gpio_direction_output(GPIO_LED_GREEN1, 0);
+					gpio_direction_output(GPIO_LED_RED2, 0);
+					gpio_direction_output(GPIO_LED_GREEN2, 1);
+					su=0;
+				}else{
+					gpio_direction_output(GPIO_LED_RED1, 0);
+					gpio_direction_output(GPIO_LED_GREEN1, 1);
+					gpio_direction_output(GPIO_LED_RED2, 1);
+					gpio_direction_output(GPIO_LED_GREEN2, 0);
+					su=1;
+				}
+				mdelay(500);
+			}
+			break;
+		case 1:
+			/* EEPROM ERROR */
+			while(1){
+				if (su){
+					gpio_direction_output(GPIO_LED_RED1, 1);
+					gpio_direction_output(GPIO_LED_GREEN1, 1);
+					gpio_direction_output(GPIO_LED_RED2, 0);
+					gpio_direction_output(GPIO_LED_GREEN2, 0);
+					su=0;
+				}else{
+					gpio_direction_output(GPIO_LED_RED1, 0);
+					gpio_direction_output(GPIO_LED_GREEN1, 0);
+					gpio_direction_output(GPIO_LED_RED2, 1);
+					gpio_direction_output(GPIO_LED_GREEN2, 1);
+					su=1;
+				}
+				mdelay(500);
+			}
+			break;
+		case 2:
+			/* SDRAM ANY CHIP ERROR */
+			while(1){
+				if (su){
+					gpio_direction_output(GPIO_LED_RED1, 1);
+					gpio_direction_output(GPIO_LED_GREEN1, 1);
+					gpio_direction_output(GPIO_LED_RED2, 0);
+					gpio_direction_output(GPIO_LED_GREEN2, 0);
+					su=0;
+				}else{
+					gpio_direction_output(GPIO_LED_RED1, 0);
+					gpio_direction_output(GPIO_LED_GREEN1, 0);
+					gpio_direction_output(GPIO_LED_RED2, 0);
+					gpio_direction_output(GPIO_LED_GREEN2, 0);
+					su=1;
+				}
+				mdelay(500);
+			}
+			break;
+	}
+}
+
+int test_i2c(void){
+
+	puts("Testing I2C...\n");
+	/* First we will test I2C */
+	if (setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1)){
+		puts("I2C: Bus 2 Error\n");
+		return 1;
+	}
+	if(setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2)){
+		puts("I2C: Bus 3 Error\n");
+		return 1;
+	}
+	mdelay(2);
 	return 0;
 }
 
-int board_init(void)
+uint8_t test_SDRAM(void)
+{
+	//dcache_disable();
+	int i = 0;
+	uint8_t result = 0;
+	uint64_t* file1 = 0;
+	uint64_t* file2 = 0;
+	uint64_t* file3 = 0;
+	uint64_t* file4 = 0;
+	int crc_value1 = 0;
+	int crc_value2 = 0;
+	int crc_value3 = 0;
+	int crc_value4 = 0;
+	int bytes = 1*1024*1024;
+
+	file1 = (uint64_t*) 0x20000000;
+	file2 = (uint64_t*) 0x40000000;
+	file3 = (uint64_t*) 0x60000000;
+	file4 = (uint64_t*) 0x80000000;
+
+/*
+	for(i=0; i<bytes;i++){
+		file1[i] = i%16;
+		file2[i] = i%16;
+		file3[i] = i%16;
+		file4[i] = i%16;
+	}
+*/
+	for(i=0; i<bytes;i++){
+		switch (i%6) {
+			case 0:
+				file1[i] = 0x0000AAAAULL;
+				file2[i] = (0x33330000ULL << 16);
+				file3[i] = (0x0000AAAAULL << 32);
+				file4[i] = (0x33330000ULL << 48);
+				break;
+			case 1:
+				file1[i] = 0x00005555ULL;
+				file2[i] = (0x99990000ULL << 16);
+				file3[i] = (0x00005555ULL << 32);
+				file4[i] = (0x99990000ULL << 48);
+				break;
+			case 2:
+				file1[i] = 0x0000CCCCULL;
+				file2[i] = (0x66660000ULL << 16);
+				file3[i] = (0x0000CCCCULL << 32);
+				file4[i] = (0x66660000ULL << 48);
+				break;
+			case 3:
+				file1[i] = 0x0000AAAAULL;
+				file2[i] = (0x33330000ULL << 16);
+				file3[i] = (0x0000AAAAULL << 32);
+				file4[i] = (0x00003333ULL << 48);
+				break;
+			case 4:
+				file1[i] = 0x00005555ULL;
+				file2[i] = (0x99990000ULL << 16);
+				file3[i] = (0x00005555ULL << 32);
+				file4[i] = (0x00009999ULL << 48);
+				break;
+			case 5:
+				file1[i] = 0x0000CCCCULL;
+				file2[i] = (0x66660000ULL << 16);
+				file3[i] = (0x0000CCCCULL << 32);
+				file4[i] = (0x66660000ULL << 48);
+				break;
+			default:
+				puts("Test RAM error \n");
+		}		
+	}
+
+	/* crc file 1 - CHIP 1 */
+	crc_value1 = crc32(0, (const unsigned char*) file1, bytes);
+	/* crc file 2 - CHIP 2 */
+	crc_value2 = crc32(0, (const unsigned char*) file2, bytes);
+	/* crc file 3 - CHIP 3 */
+	crc_value3 = crc32(0, (const unsigned char*) file3, bytes);
+	/* crc file 4 - CHIP 4 */
+	crc_value4 = crc32(0, (const unsigned char*) file4, bytes);
+
+  	printf("CHIP 1 U500 crc32: 0x%x \n", crc_value1);
+  	printf("CHIP 2 U501 crc32: 0x%x \n", crc_value2);
+ 	printf("CHIP 3 U502 crc32: 0x%x \n", crc_value3);
+  	printf("CHIP 4 U503 crc32: 0x%x \n", crc_value4);
+
+  	//dcache_enable();
+
+  	if(crc_value1 != KNOWN_CRC_CUSTOM_1MB_1){
+  		/* Chip 1 Fail */
+  		result = result + 0x01;
+  	}
+  	if(crc_value2 != KNOWN_CRC_CUSTOM_1MB_2){
+  		/* Chip 2 Fail */
+  		result = result + 0x02;
+  	}
+  	if(crc_value3 != KNOWN_CRC_CUSTOM_1MB_3){
+  		/* Chip 3 Fail */
+  		result = result + 0x04;
+  	}
+  	if(crc_value4 != KNOWN_CRC_CUSTOM_1MB_4){
+  		/* Chip 4 Fail */
+  		result = result + 0x08;
+  	}
+
+  	/* RESULT */
+  	return result;
+}
+
+int test_MMC(int who)
 {
+	struct mmc *mmc;
+
+	if(who){
+	/* eMMC case */
+	mmc = find_mmc_device(1);
+	}else{
+	/* SD case */
+	mmc = find_mmc_device(0);
+	}
+
+	if (!mmc){
+		return 1;
+	}
+
+	if (mmc_init(mmc)){
+		return 1;
+	}
 
-	/* configure LEDS - UBOOT = 2 YELLOW */
+	if (IS_SD(mmc)){
+		return 0;
+	}else{
+		return 0;
+	}
+	return 0;
+}
+
+int test_ETH(void)
+{
+	net_ping_ip = string_to_ip("192.168.2.171");
+	net_ip = string_to_ip("192.168.2.101");
+	net_netmask = string_to_ip("255.255.255.0");
+	net_gateway = string_to_ip("192.168.2.1");
+
+	/* Just to avoid warning */
+	if (net_ping_ip.s_addr == 0){
+		return CMD_RET_USAGE;
+	}
+
+	/* Check if network is already down */
+	if(net_fail){
+		return 1;
+	}
+	/*
+	else{
+		if (net_loop(5) < 0) {
+			printf("ping failed; host 192.168.2.171 is not alive\n");
+			return 1;
+		}
+	}
+	*/
+	return 0;
+}
+
+int board_init(void)
+{
+	/* Configure LEDS - UBOOT = 2 YELLOW */
 	gpio_direction_output(GPIO_LED_RED1, 1);
 	gpio_direction_output(GPIO_LED_GREEN1, 1);
 	gpio_direction_output(GPIO_LED_RED2, 1);
@@ -456,7 +710,6 @@ int board_init(void)
 #ifdef CONFIG_USB_EHCI_MX6
 	setup_usb();
 #endif
-
 	return 0;	
 }
 
@@ -491,46 +744,8 @@ static inline unsigned int pcb_version(void)
 }
 
 int board_late_init(void)
-{	
-
-	u32 crc_value = 0;
-	u32 crc_save_value;
-
-    if(check_eeprom() != 0){
-	printf("EEPROM: not found\n");
-    }else{
-		/* Read configuration from eeprom */
-		if(eeprom46_read_setup(0, (char*) &igep0046_eeprom_config, sizeof(struct igep_mf_setup)))
-	  		printf("EEPROM: read fail\n");	
-		/* Verify crc32 */
-
-	  	printf("EEPROM: read %d bytes \n", sizeof(struct igep_mf_setup));
-	  	printf("---------------------------- |!| IGEP STRUCT |!| ----------------------------\n");
-  		printf("magic_id: 0x%x \n", igep0046_eeprom_config.magic_id);
-  		printf("crc32: 0x%x \n", igep0046_eeprom_config.crc32);
-  		printf("board_uuid: %.36s \n", igep0046_eeprom_config.board_uuid);
-  		printf("board_pid: %.16s \n", igep0046_eeprom_config.board_pid);
-  		printf("model: %.8s \n", igep0046_eeprom_config.model);
-  		printf("variant: %.9s \n", igep0046_eeprom_config.variant);
-		printf("manf_of: %.6s \n", igep0046_eeprom_config.manf_of);
-  		printf("manf_timestamp: %.19s \n", igep0046_eeprom_config.manf_timestamp);
-		printf("bmac0: %.17s \n", igep0046_eeprom_config.bmac0);
-  		printf("bmac1: %.17s \n", igep0046_eeprom_config.bmac1);
-	  	printf("-----------------------------------------------------------------------------\n");
-
-
-	   	crc_save_value = igep0046_eeprom_config.crc32;
-	   	igep0046_eeprom_config.crc32 = 0;
-	   	crc_value = crc32(0, (const unsigned char*) &igep0046_eeprom_config, sizeof(struct igep_mf_setup));
-  		printf("crc32 calculated: 0x%x \n", crc_value);
-		if(crc_save_value != crc_value){
-       		printf("EEPROM: CRC32 failed. Loading default MAC\n");				
-		}else{
-	    	printf("EEPROM: CRC32 OK! Loading MAC from eeprom\n");	       		
-	  		igep_eeprom_valid = 1;
-		}
-	}
-
+{
+	uint64_t cpuid = 0;
 	checkboard();
 	switch (pcb_version()) {
 		case PCB_REV_A:
@@ -570,8 +785,111 @@ int board_late_init(void)
 			setenv("fdt_file", "");
 			break;
 	}
+
+	/* Get CPU ID */
+	cpuid = ((uint64_t)readl(0x21bc420) << 32) | (readl(0x21bc410));
+	printf("CPU ID: 0x%llx \n",cpuid);
+	return 0;
+}
+
+#ifdef CONFIG_LAST_STAGE_INIT
+int last_stage_init(void){
+	
+	/* This is the function that will be called last before running bootcmd u-boot */
+	uint16_t test = 0;
+	//uint8_t ramtest = 0;
+	uint64_t cpuid = 0;
+	
+	/* We need to read SPL eeprom struct to acquire whose test have already being done */
+	puts("---------------------------- |!| ISEE UBOOT TEST START |!| ----------------------------\n");
+	/* Get SPL last test */
+	test = load_test(SPL_MAGIC_ID_COUNTER);
+	if (test == 0x4000){
+		puts("SPL GET TEST FAILED.\n");
+
+	}else if (test == 0xfff0){
+		puts("I2C OK.\n");
+		puts("EEPROM OK.\n");
+		puts("POWER OK.\n");
+		puts("CPU OK.\n");
+		puts("SD OK.\n");
+		puts("REV OK.\n");
+		puts("IRAM OK.\n");
+		puts("SDRAM OK.\n");
+		puts("CPUID OK.\n");
+	}else{
+		puts("SOME SPL TEST FAILED, PERFORM MANUAL CHECK.\n");
+	}
+
+	/* Test RAM Now this will be done in SPL !!!
+	ramtest = test_SDRAM();
+
+	if((ramtest & 0x01) == 0x01){
+		puts("SDRAM CHIP 1 FAIL.\n");
+	}
+
+	if((ramtest & 0x02) == 0x02){
+		puts("SDRAM CHIP 2 FAIL.\n");
+	}
+
+	if((ramtest & 0x04) == 0x04){
+		puts("SDRAM CHIP 3 FAIL.\n");
+	}
+	
+	if((ramtest & 0x08) == 0x08){
+		puts("SDRAM CHIP 4 FAIL.\n");
+	}
+
+	if(!ramtest){
+		puts("RAM OK.\n");
+		test = test + 0xF0;
+	}else{
+		puts("RAM FAIL.\n");
+	}
+	*/
+
+	/* Test eMMC */
+	if(test_MMC(1)){
+		puts("eMMC FAIL.\n");
+	}else{
+		puts("eMMC OK.\n");
+		test = test + 0x08;
+	}
+
+	/* Test Ethernet */
+	if(test_ETH()){
+		puts("Ethernet FAIL.\n");
+	}else{
+		puts("Ethernet OK.\n");
+		test = test + 0x04;
+	}
+
+	/*
+	test_SATA();
+	test_USB();
+	*/
+	
+	/* We will reserve 2 bits for future test development like SATA, USB */
+	/* So for now add test the last 3 bits to 1 to forma a 0xffff if everything is ok */
+	test = test + 0x03;
+
+	/* Get CPU ID */
+	cpuid = ((uint64_t)readl(0x21bc420) << 32) | (readl(0x21bc410));
+	puts("CPUID OK.\n");
+
+	printf("U-BOOT Test Result: 0x%x\n",test);
+
+	/* Save Results to EEPROM */
+	if (save_test(test,UB_MAGIC_ID,cpuid)){
+		puts("ISEE U-BOOT TEST FAIL.\n");
+	}else{
+		puts("ISEE U-BOOT TEST OK.\n");
+	}
+
+	/* Let test process continue, bootcmd take us to kernel load via tftp and jump to it */
 	return 0;
 }
+#endif
 
 #ifdef CONFIG_LDO_BYPASS_CHECK
 /* TODO, use external pmic, for now always ldo_enable */
@@ -942,6 +1260,12 @@ void board_init_f(ulong dummy)
 	/* iomux and setup of UART and leds */
 	board_early_init_f();
 
+	/* configure LEDS - SPL = 1 YELLOW */
+	gpio_direction_output(GPIO_LED_RED1, 1);
+	gpio_direction_output(GPIO_LED_GREEN1, 1);
+	gpio_direction_output(GPIO_LED_RED2, 0);
+	gpio_direction_output(GPIO_LED_GREEN2, 0);
+
 	/* setup GP timer */
 	timer_init();
 
@@ -969,11 +1293,56 @@ void board_init_f(ulong dummy)
 /* called from board_init_r after gd setup if CONFIG_SPL_BOARD_INIT defined */
 /* its our chance to print info about boot device */
 void spl_board_init(void)
-{
+{	
+	u32 boot_device = 0;
+	uint64_t cpuid = 0;
+	u16 test = 0;
+	uint8_t ramtest = 0;
 
-	/* determine boot device from SRC_SBMR1 (BOOT_CFG[4:1]) or SRC_GPR9 */
-	u32 boot_device = spl_boot_device();
+	/* Minimal init sequence for pmic setup of igep imx6 boards */
+	#ifdef CONFIG_BASE0040
+	reset_audio();
+	#endif
 
+	/* First we will test I2C */
+	puts("---------------------------- |!| ISEE SPL TEST START |!| ----------------------------\n");
+
+	/* Test I2C */	
+	#ifdef CONFIG_SYS_I2C
+	if(test_i2c()){
+		puts("I2C FAIL.\n");
+		error_loop(0);
+	}else{
+		puts("I2C OK.\n");
+	}
+	#endif
+
+	/* Test EEPROM */
+	if(test_eeprom()){
+		puts("EEPROM FAIL.\n");
+		error_loop(1);
+	}else{
+		puts("EEPROM OK.\n");
+	}
+	mdelay(2);
+
+	/* If we are here we put test variable to 11000000 00000000 */ 
+	test = 0xC000;
+
+	/* Next we would want to know the counter just for control purpose */
+	//test_counter_check(SPL_TEST_COUNTER_OFF);
+
+	/* Test Power, PMIC */
+	if(power_init_board()){
+		puts("POWER FAIL.\n");
+	}else{
+		puts("POWER OK.\n");
+		/* Test = 11100000 00000000 */
+		test = test + 0x2000;
+	}
+
+	/* determine boot device from SRC_SBMR1 (BOOT_CFG[4:1]) or SRC_GPR9 */
+	boot_device = spl_boot_device();
 	switch (boot_device) {
 	case BOOT_DEVICE_MMC1:
 		puts("Booting from MMC\n");
@@ -987,27 +1356,78 @@ void spl_board_init(void)
 	default:
 		puts("Unknown boot device\n");
 	}
+
+	/* If we are here (imx6) case CPU and SD should be working */
+	puts("CPU OK.\n");
+	puts("SD OK.\n");
+	/* Test = 11111000 00000000 */
+	test = test + 0x1800;
 	
-	/* Minimal init sequence for pmic setup of igep imx6 boards */
-	#ifdef CONFIG_BASE0040
-	reset_audio();
-	#endif
+	/* Test Revision PINs */
+	if (!(pcb_version() == TEST_REVISION)) {
+		puts("REV FAIL.\n");
+	}else{
+		puts("REV OK.\n");
+		/* Test = 11111100 00000000 */
+		test = test + 0x400;
+	}
 
-	#ifdef CONFIG_SYS_I2C
-	setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
-	setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
-	mdelay(1);
-	#endif
+	/* Internal RAM is working */
+	puts("Internal RAM OK.\n");
+	/* Test = 11111110 00000000 */
+	test = test + 0x200;
+
+	/* Test SDRAM */
+	ramtest = test_SDRAM();
+
+	if((ramtest & 0x01) == 0x01){
+		puts("SDRAM CHIP 1 FAIL.\n");
+	}
+
+	if((ramtest & 0x02) == 0x02){
+		puts("SDRAM CHIP 2 FAIL.\n");
+	}
+
+	if((ramtest & 0x04) == 0x04){
+		puts("SDRAM CHIP 3 FAIL.\n");
+	}
+	
+	if((ramtest & 0x08) == 0x08){
+		puts("SDRAM CHIP 4 FAIL.\n");
+	}
+
+	if(!ramtest){
+		puts("SDRAM OK.\n");
+		test = test + 0xF0;
+	}else{
+		puts("SDRAM FAIL.\n");
+		/* Do not jump to UBOOT until SDRAM hardware is good */
+		error_loop(2);
+	}
+
+	/* Get CPU ID */
+	cpuid = ((uint64_t)readl(0x21bc420) << 32) | (readl(0x21bc410));
+	puts("CPUID OK.\n");
+	/* Test = 11111111 00000000 */
+	test = test + 0x100;
 
-	/* PMIC init */
-	power_init_board();
+	/* Print Test Result */
+	printf("SPL Test Result: 0x%x\n",test);
+
+	/* Save Results to EEPROM */
+	if (save_test(test,SPL_MAGIC_ID,cpuid)){
+		puts("ISEE SPL TEST FAIL.\n");
+	}else{
+		puts("ISEE SPL TEST OK.\n");
+	}
+	/* Jump to U-BOOT */
 }
 
 #ifdef CONFIG_SPL_OS_BOOT
-/* return 1 if we wish to boot to uboot vs os (falcon mode) */
+/* return 1 if we wish to boot to uboot vs 0 if we wish to falcon mode */
 int spl_start_uboot(void)
 {
-	return 0;
+	return 1;
 }
 
 void spl_board_prepare_for_linux(void)
@@ -1053,4 +1473,4 @@ void spl_board_prepare_for_linux(void)
 }
 
 #endif
-#endif
+#endif
\ No newline at end of file
diff --git a/board/isee/igep0046/igep0046_eeprom.c b/board/isee/igep0046/igep0046_eeprom.c
deleted file mode 100644
index d484d23..0000000
--- a/board/isee/igep0046/igep0046_eeprom.c
+++ /dev/null
@@ -1,71 +0,0 @@
-/*
- * Copyright (C) 2016 ISEE 2007 SL - http://www.isee.biz
- *
- * EEPROM support source file for IGEP0046 board
- *
- * Author: Jose Miguel Sanchez Sanabria <jsanabria@iseebcn.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <i2c.h>
-#include <asm/arch/sys_proto.h>
-
-
-int eeprom46_write_setup (uint8_t s_addr, const char* data, u32 size)
-{
-    u32 i;
-    u32 remain = size % 32;
-    u32 blocks = size / 32;
-    for (i=0; i < blocks; i++){
-        if(i2c_write(CONFIG_SYS_I2C_EEPROM_ADDR, s_addr + (i*32), 2, (uint8_t*) data + (i*32), 32)){
-            return -1;
-        }
-        udelay(5000);
-    }
-    if(remain > 0){
-        if(i2c_write(CONFIG_SYS_I2C_EEPROM_ADDR, s_addr + (i*32), 2, (uint8_t*) data + (i*32), remain))
-            return -1;
-        else
-            udelay(5000);
-    }
-    return 0;
-}
-
-int eeprom46_read_setup (uint8_t s_addr, char* data, u32 size)
-{
-    u32 i;
-    u32 remain = size % 32;
-    u32 blocks = size / 32;
-    for (i=0; i < blocks; i++){
-        if(i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, s_addr + (i*32), 2, (uint8_t*) data + (i*32), 32)){
-            return -1;
-        }
-    }
-    if(remain > 0)
-        if(i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, s_addr + (i*32), 2, (uint8_t*) data + (i*32), remain))
-            return -1;
-    return 0;
-}
-
-int check_eeprom (void)
-{
-    i2c_set_bus_num(CONFIG_SYS_I2C_EEPROM_BUS);
-    /* Check if baseboard eeprom is available */
-	if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
-		printf("Could not probe the EEPROM at 0x%x\n",
-		       CONFIG_SYS_I2C_EEPROM_ADDR);
-		return -1;
-	}
-	return 0;
-}
-
-unsigned int parse_char(char c)
-{
-    if ('0' <= c && c <= '9') return c - '0';
-    if ('a' <= c && c <= 'f') return 10 + c - 'a';
-    if ('A' <= c && c <= 'F') return 10 + c - 'A';
-    
-    return 0;
-}
\ No newline at end of file
diff --git a/board/isee/igep0046/igep0046_eeprom.h b/board/isee/igep0046/igep0046_eeprom.h
deleted file mode 100644
index df739e0..0000000
--- a/board/isee/igep0046/igep0046_eeprom.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/*
- * Copyright (C) 2016 ISEE 2007 SL - http://www.isee.biz
- *
- * 0046 EEPROM Definitions
- *
- * Author: Jose Miguel Sanchez Sanabria <jsanabria@iseebcn.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __EEPROM_BOARD_HELPER__
-#define __EEPROM_BOARD_HELPER__
-
-int eeprom46_write_setup (uint8_t s_addr, const char* data, u32 size);
-int eeprom46_read_setup (uint8_t s_addr, char* data, u32 size);
-int check_eeprom (void);
-unsigned int parse_char(char c);
-#endif
diff --git a/board/isee/igep0046/mx6dl_igep0046_4x512_nt.cfg b/board/isee/igep0046/mx6dl_igep0046_4x512_nt.cfg
index 21e319f..9dc1d8d 100644
--- a/board/isee/igep0046/mx6dl_igep0046_4x512_nt.cfg
+++ b/board/isee/igep0046/mx6dl_igep0046_4x512_nt.cfg
@@ -1,204 +1,203 @@
-/*

- * Copyright (C) 2016 ISEE 2007 SL - http://www.isee.biz

- *

- * SPDX-License-Identifier:	GPL-2.0+

- *

- * Refer docs/README.imxmage for more details about how-to configure

- * and create imximage boot image

- *

- * The syntax is taken as close as possible with the kwbimage

- */

-

-/* image version */

-

-IMAGE_VERSION 2

-

-/*

- * Boot Device : one of

- * spi, sd (the board has no nand neither onenand)

- */

-

-BOOT_FROM	sd

-

-/*

- * Device Configuration Data (DCD)

- *

- * Each entry must have the format:

- * Addr-type           Address        Value

- *

- * where:

- *	Addr-type register length (1,2 or 4	bytes)

- *	Address	  absolute address of the register

- *	value	  value to be stored in the register

- */

-

-//=============================================================================			

-// Enable all clocks (they are disabled by ROM code)			

-//=============================================================================			

-DATA 4	0x020c4068 0xffffffff	

-DATA 4	0x020c406c 0xffffffff	

-DATA 4	0x020c4070 0xffffffff	

-DATA 4	0x020c4074 0xffffffff	

-DATA 4	0x020c4078 0xffffffff	

-DATA 4	0x020c407c 0xffffffff	

-DATA 4	0x020c4080 0xffffffff	

-DATA 4	0x020c4084 0xffffffff	

-			

-//=============================================================================			

-// IOMUX			

-//=============================================================================			

-//DDR IO TYPE:			

-DATA 4	0x020e0774 0x000C0000	// IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE 

-DATA 4	0x020e0754 0x00000000	// IOMUXC_SW_PAD_CTL_GRP_DDRPKE 

-			

-//CLOCK:			

-DATA 4	0x020e04ac 0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_0

-DATA 4	0x020e04b0 0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_1

-			

-//ADDRESS:			

-DATA 4	0x020e0464 0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS

-DATA 4	0x020e0490 0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS

-DATA 4	0x020e074c 0x00000030	// IOMUXC_SW_PAD_CTL_GRP_ADDDS 

-			

-//Control:			

-DATA 4	0x020e0494 0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET

-DATA 4	0x020e04a0 0x00000000	// IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2 - DSE can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_CTLDS

-DATA 4	0x020e04b4 0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT0

-DATA 4	0x020e04b8 0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT1

-DATA 4	0x020e076c 0x00000030	// IOMUXC_SW_PAD_CTL_GRP_CTLDS 

-			

-//Data Strobes:			

-DATA 4	0x020e0750 0x00020000	// IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL 

-DATA 4	0x020e04bc 0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0 

-DATA 4	0x020e04c0 0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1 

-DATA 4	0x020e04c4 0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2 

-DATA 4	0x020e04c8 0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3 

-DATA 4	0x020e04cc 0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4 

-DATA 4	0x020e04d0 0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5 

-DATA 4	0x020e04d4 0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6 

-DATA 4	0x020e04d8 0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7 

-			

-//Data:			

-DATA 4	0x020e0760 0x00020000	// IOMUXC_SW_PAD_CTL_GRP_DDRMODE

-DATA 4	0x020e0764 0x00000030	// IOMUXC_SW_PAD_CTL_GRP_B0DS 

-DATA 4	0x020e0770 0x00000030	// IOMUXC_SW_PAD_CTL_GRP_B1DS 

-DATA 4	0x020e0778 0x00000030	// IOMUXC_SW_PAD_CTL_GRP_B2DS 

-DATA 4	0x020e077c 0x00000030	// IOMUXC_SW_PAD_CTL_GRP_B3DS 

-DATA 4	0x020e0780 0x00000030	// IOMUXC_SW_PAD_CTL_GRP_B4DS 

-DATA 4	0x020e0784 0x00000030	// IOMUXC_SW_PAD_CTL_GRP_B5DS 

-DATA 4	0x020e078c 0x00000030	// IOMUXC_SW_PAD_CTL_GRP_B6DS 

-DATA 4	0x020e0748 0x00000030	// IOMUXC_SW_PAD_CTL_GRP_B7DS 

-			

-DATA 4	0x020e0470 0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0

-DATA 4	0x020e0474 0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1

-DATA 4	0x020e0478 0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2

-DATA 4	0x020e047c 0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3

-DATA 4	0x020e0480 0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4

-DATA 4	0x020e0484 0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5

-DATA 4	0x020e0488 0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6

-DATA 4	0x020e048c 0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7

-			

-			

-//=============================================================================			

-// DDR Controller Registers			

-//=============================================================================			

-// Manufacturer:	Samsung		

-// Device Part Number:	K4B4G1646D-BMK00CV		

-// Clock Freq.: 	MHz		

-// Density per CS in Gb: 	16		

-// Chip Selects used:	1		

-// Number of Banks:	8		

-// Row address:    	15		

-// Column address: 	10		

-// Data bus width	64		

-//=============================================================================			

-DATA 4	0x021b001c 0x00008000	MMDC0_MDSCR, set the Configuration request bit during MMDC set up

-			

-//=============================================================================			

-// Calibration setup.			

-//=============================================================================			

-DATA 4	0x021b0800 0xA1390003	// DDR_PHY_P0_MPZQHWCTRL, enable both one-time & periodic HW ZQ calibration.

-			

-// For target board, may need to run write leveling calibration to fine tune these settings.			

-DATA 4	0x021b080c 0x00530056	

-DATA 4	0x021b0810 0x00440053	

-DATA 4	0x021b480c 0x002B002B	

-DATA 4	0x021b4810 0x0028003F	

-			

-////Read DQS Gating calibration			

-DATA 4	0x021b083c 0x021C021C	// MPDGCTRL0 PHY0

-DATA 4	0x021b0840 0x02140214	// MPDGCTRL1 PHY0

-DATA 4	0x021b483c 0x0178017C	// MPDGCTRL0 PHY1

-DATA 4	0x021b4840 0x016C0170	// MPDGCTRL1 PHY1

-			

-//Read calibration			

-DATA 4	0x021b0848 0x46484C48	// MPRDDLCTL PHY0

-DATA 4	0x021b4848 0x42424842	// MPRDDLCTL PHY1

-			

-//Write calibration                     			

-DATA 4	0x021b0850 0x3434302E	// MPWRDLCTL PHY0

-DATA 4	0x021b4850 0x3A303830	// MPWRDLCTL PHY1

-			

-//read data bit delay: (3 is the reccommended default value, although out of reset value is 0)			

-DATA 4	0x021b081c 0x33333333	// DDR_PHY_P0_MPREDQBY0DL3

-DATA 4	0x021b0820 0x33333333	// DDR_PHY_P0_MPREDQBY1DL3

-DATA 4	0x021b0824 0x33333333	// DDR_PHY_P0_MPREDQBY2DL3

-DATA 4	0x021b0828 0x33333333	// DDR_PHY_P0_MPREDQBY3DL3

-DATA 4	0x021b481c 0x33333333	// DDR_PHY_P1_MPREDQBY0DL3

-DATA 4	0x021b4820 0x33333333	// DDR_PHY_P1_MPREDQBY1DL3

-DATA 4	0x021b4824 0x33333333	// DDR_PHY_P1_MPREDQBY2DL3

-DATA 4	0x021b4828 0x33333333	// DDR_PHY_P1_MPREDQBY3DL3

-			

-//For i.mx6qd parts of versions A & B (v1.0, v1.1), uncomment the following lines. For version C (v1.2), keep commented			

-//DATA 4	0x021b08c0 0x24911492	// fine tune SDCLK duty cyc to low - seen to improve measured duty cycle of i.mx6

-//DATA 4	0x021b48c0 0x24911492	

-			

-// Complete calibration by forced measurement:                  			

-DATA 4	0x021b08b8 0x00000800	// DDR_PHY_P0_MPMUR0, frc_msr

-DATA 4	0x021b48b8 0x00000800	// DDR_PHY_P0_MPMUR0, frc_msr

-//=============================================================================			

-// Calibration setup end			

-//=============================================================================			

-			

-//MMDC init: 			

-DATA 4	0x021b0004 0x0002002D	// MMDC0_MDPDC

-DATA 4	0x021b0008 0x00333040	// MMDC0_MDOTC

-DATA 4	0x021b000c 0x676B52F3	// MMDC0_MDCFG0

-DATA 4	0x021b0010 0xB66D8B63	// MMDC0_MDCFG1

-DATA 4	0x021b0014 0x01FF00DB	// MMDC0_MDCFG2

-			

-//MDMISC: RALAT kept to the high level of 5. 			

-//MDMISC: consider reducing RALAT if your 528MHz board design allow that. Lower RALAT benefits: 			

-//a. better operation at low frequency, for LPDDR2 freq < 100MHz, change RALAT to 3			

-//b. Small performence improvment 			

-DATA 4	0x021b0018 0x00011740	// MMDC0_MDMISC

-DATA 4	0x021b001c 0x00008000	// MMDC0_MDSCR, set the Configuration request bit during MMDC set up

-DATA 4	0x021b002c 0x000026D2	// MMDC0_MDRWD

-DATA 4	0x021b0030 0x006B1023	// MMDC0_MDOR

-DATA 4	0x021b0040 0x00000047	// Chan0 CS0_END 

-DATA 4	0x021b0000 0x841A0000	// MMDC0_MDCTL

-			

-//Mode register writes                 			

-DATA 4	0x021b001c 0x02008032	// MMDC0_MDSCR, MR2 write, CS0

-DATA 4	0x021b001c 0x00008033	// MMDC0_MDSCR, MR3 write, CS0

-DATA 4	0x021b001c 0x00048031	// MMDC0_MDSCR, MR1 write, CS0

-DATA 4	0x021b001c 0x15208030	// MMDC0_MDSCR, MR0write, CS0

-DATA 4	0x021b001c 0x04008040	// MMDC0_MDSCR, ZQ calibration command sent to device on CS0

-			

-//DATA 4	0x021b001c 0x0200803A	// MMDC0_MDSCR, MR2 write, CS1

-//DATA 4	0x021b001c 0x0000803B	// MMDC0_MDSCR, MR3 write, CS1

-//DATA 4	0x021b001c 0x00048039	// MMDC0_MDSCR, MR1 write, CS1

-//DATA 4	0x021b001c 0x15208038	// MMDC0_MDSCR, MR0write, CS1

-//DATA 4	0x021b001c 0x04008048	// MMDC0_MDSCR, ZQ calibration command sent to device on CS1

-			

-DATA 4	0x021b0020 0x00007800	// MMDC0_MDREF

-			

-DATA 4	0x021b0818 0x00022227	// DDR_PHY_P0_MPODTCTRL

-DATA 4	0x021b4818 0x00022227	// DDR_PHY_P1_MPODTCTRL

-			

-DATA 4	0x021b0004 0x0002556D	// MMDC0_MDPDC now SDCTL power down enabled

-			

-DATA 4	0x021b0404 0x00011006	// MMDC0_MAPSR ADOPT power down enabled, MMDC will enter automatically to self-refresh while the number of idle cycle reached.

-			

-DATA 4	0x021b001c 0x00000000	// MMDC0_MDSCR, clear this register (especially the configuration bit as initialization is complete)

-

+/*
+ * Copyright (C) 2016 ISEE 2007 SL - http://www.isee.biz
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+/* image version */
+
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi, sd (the board has no nand neither onenand)
+ */
+
+BOOT_FROM	sd
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type           Address        Value
+ *
+ * where:
+ *	Addr-type register length (1,2 or 4	bytes)
+ *	Address	  absolute address of the register
+ *	value	  value to be stored in the register
+ */
+
+//=============================================================================			
+// Enable all clocks (they are disabled by ROM code)			
+//=============================================================================			
+DATA 4	0x020c4068 0xffffffff	
+DATA 4	0x020c406c 0xffffffff	
+DATA 4	0x020c4070 0xffffffff	
+DATA 4	0x020c4074 0xffffffff	
+DATA 4	0x020c4078 0xffffffff	
+DATA 4	0x020c407c 0xffffffff	
+DATA 4	0x020c4080 0xffffffff	
+DATA 4	0x020c4084 0xffffffff	
+			
+//=============================================================================			
+// IOMUX			
+//=============================================================================			
+//DDR IO TYPE:			
+DATA 4	0x020e0774 0x000C0000	// IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE 
+DATA 4	0x020e0754 0x00000000	// IOMUXC_SW_PAD_CTL_GRP_DDRPKE 
+			
+//CLOCK:			
+DATA 4	0x020e04ac 0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_0
+DATA 4	0x020e04b0 0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_1
+			
+//ADDRESS:			
+DATA 4	0x020e0464 0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS
+DATA 4	0x020e0490 0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS
+DATA 4	0x020e074c 0x00000030	// IOMUXC_SW_PAD_CTL_GRP_ADDDS 
+			
+//Control:			
+DATA 4	0x020e0494 0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET
+DATA 4	0x020e04a0 0x00000000	// IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2 - DSE can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_CTLDS
+DATA 4	0x020e04b4 0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT0
+DATA 4	0x020e04b8 0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT1
+DATA 4	0x020e076c 0x00000030	// IOMUXC_SW_PAD_CTL_GRP_CTLDS 
+			
+//Data Strobes:			
+DATA 4	0x020e0750 0x00020000	// IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL 
+DATA 4	0x020e04bc 0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0 
+DATA 4	0x020e04c0 0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1 
+DATA 4	0x020e04c4 0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2 
+DATA 4	0x020e04c8 0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3 
+DATA 4	0x020e04cc 0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4 
+DATA 4	0x020e04d0 0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5 
+DATA 4	0x020e04d4 0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6 
+DATA 4	0x020e04d8 0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7 
+			
+//Data:			
+DATA 4	0x020e0760 0x00020000	// IOMUXC_SW_PAD_CTL_GRP_DDRMODE
+DATA 4	0x020e0764 0x00000030	// IOMUXC_SW_PAD_CTL_GRP_B0DS 
+DATA 4	0x020e0770 0x00000030	// IOMUXC_SW_PAD_CTL_GRP_B1DS 
+DATA 4	0x020e0778 0x00000030	// IOMUXC_SW_PAD_CTL_GRP_B2DS 
+DATA 4	0x020e077c 0x00000030	// IOMUXC_SW_PAD_CTL_GRP_B3DS 
+DATA 4	0x020e0780 0x00000030	// IOMUXC_SW_PAD_CTL_GRP_B4DS 
+DATA 4	0x020e0784 0x00000030	// IOMUXC_SW_PAD_CTL_GRP_B5DS 
+DATA 4	0x020e078c 0x00000030	// IOMUXC_SW_PAD_CTL_GRP_B6DS 
+DATA 4	0x020e0748 0x00000030	// IOMUXC_SW_PAD_CTL_GRP_B7DS 
+			
+DATA 4	0x020e0470 0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0
+DATA 4	0x020e0474 0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1
+DATA 4	0x020e0478 0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2
+DATA 4	0x020e047c 0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3
+DATA 4	0x020e0480 0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4
+DATA 4	0x020e0484 0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5
+DATA 4	0x020e0488 0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6
+DATA 4	0x020e048c 0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7
+			
+			
+//=============================================================================			
+// DDR Controller Registers			
+//=============================================================================			
+// Manufacturer:	Samsung		
+// Device Part Number:	K4B4G1646D-BMK00CV		
+// Clock Freq.: 	MHz		
+// Density per CS in Gb: 	16		
+// Chip Selects used:	1		
+// Number of Banks:	8		
+// Row address:    	15		
+// Column address: 	10		
+// Data bus width	64		
+//=============================================================================			
+DATA 4	0x021b001c 0x00008000	MMDC0_MDSCR, set the Configuration request bit during MMDC set up
+			
+//=============================================================================			
+// Calibration setup.			
+//=============================================================================			
+DATA 4	0x021b0800 0xA1390003	// DDR_PHY_P0_MPZQHWCTRL, enable both one-time & periodic HW ZQ calibration.
+			
+// For target board, may need to run write leveling calibration to fine tune these settings.			
+DATA 4	0x021b080c 0x00530056	
+DATA 4	0x021b0810 0x00440053	
+DATA 4	0x021b480c 0x002B002B	
+DATA 4	0x021b4810 0x0028003F	
+			
+////Read DQS Gating calibration			
+DATA 4	0x021b083c 0x021C021C	// MPDGCTRL0 PHY0
+DATA 4	0x021b0840 0x02140214	// MPDGCTRL1 PHY0
+DATA 4	0x021b483c 0x0178017C	// MPDGCTRL0 PHY1
+DATA 4	0x021b4840 0x016C0170	// MPDGCTRL1 PHY1
+			
+//Read calibration			
+DATA 4	0x021b0848 0x46484C48	// MPRDDLCTL PHY0
+DATA 4	0x021b4848 0x42424842	// MPRDDLCTL PHY1
+			
+//Write calibration                     			
+DATA 4	0x021b0850 0x3434302E	// MPWRDLCTL PHY0
+DATA 4	0x021b4850 0x3A303830	// MPWRDLCTL PHY1
+			
+//read data bit delay: (3 is the reccommended default value, although out of reset value is 0)			
+DATA 4	0x021b081c 0x33333333	// DDR_PHY_P0_MPREDQBY0DL3
+DATA 4	0x021b0820 0x33333333	// DDR_PHY_P0_MPREDQBY1DL3
+DATA 4	0x021b0824 0x33333333	// DDR_PHY_P0_MPREDQBY2DL3
+DATA 4	0x021b0828 0x33333333	// DDR_PHY_P0_MPREDQBY3DL3
+DATA 4	0x021b481c 0x33333333	// DDR_PHY_P1_MPREDQBY0DL3
+DATA 4	0x021b4820 0x33333333	// DDR_PHY_P1_MPREDQBY1DL3
+DATA 4	0x021b4824 0x33333333	// DDR_PHY_P1_MPREDQBY2DL3
+DATA 4	0x021b4828 0x33333333	// DDR_PHY_P1_MPREDQBY3DL3
+			
+//For i.mx6qd parts of versions A & B (v1.0, v1.1), uncomment the following lines. For version C (v1.2), keep commented			
+//DATA 4	0x021b08c0 0x24911492	// fine tune SDCLK duty cyc to low - seen to improve measured duty cycle of i.mx6
+//DATA 4	0x021b48c0 0x24911492	
+			
+// Complete calibration by forced measurement:                  			
+DATA 4	0x021b08b8 0x00000800	// DDR_PHY_P0_MPMUR0, frc_msr
+DATA 4	0x021b48b8 0x00000800	// DDR_PHY_P0_MPMUR0, frc_msr
+//=============================================================================			
+// Calibration setup end			
+//=============================================================================			
+			
+//MMDC init: 			
+DATA 4	0x021b0004 0x0002002D	// MMDC0_MDPDC
+DATA 4	0x021b0008 0x00333040	// MMDC0_MDOTC
+DATA 4	0x021b000c 0x676B52F3	// MMDC0_MDCFG0
+DATA 4	0x021b0010 0xB66D8B63	// MMDC0_MDCFG1
+DATA 4	0x021b0014 0x01FF00DB	// MMDC0_MDCFG2
+			
+//MDMISC: RALAT kept to the high level of 5. 			
+//MDMISC: consider reducing RALAT if your 528MHz board design allow that. Lower RALAT benefits: 			
+//a. better operation at low frequency, for LPDDR2 freq < 100MHz, change RALAT to 3			
+//b. Small performence improvment 			
+DATA 4	0x021b0018 0x00011740	// MMDC0_MDMISC
+DATA 4	0x021b001c 0x00008000	// MMDC0_MDSCR, set the Configuration request bit during MMDC set up
+DATA 4	0x021b002c 0x000026D2	// MMDC0_MDRWD
+DATA 4	0x021b0030 0x006B1023	// MMDC0_MDOR
+DATA 4	0x021b0040 0x00000047	// Chan0 CS0_END 
+DATA 4	0x021b0000 0x841A0000	// MMDC0_MDCTL
+			
+//Mode register writes                 			
+DATA 4	0x021b001c 0x02008032	// MMDC0_MDSCR, MR2 write, CS0
+DATA 4	0x021b001c 0x00008033	// MMDC0_MDSCR, MR3 write, CS0
+DATA 4	0x021b001c 0x00048031	// MMDC0_MDSCR, MR1 write, CS0
+DATA 4	0x021b001c 0x15208030	// MMDC0_MDSCR, MR0write, CS0
+DATA 4	0x021b001c 0x04008040	// MMDC0_MDSCR, ZQ calibration command sent to device on CS0
+			
+//DATA 4	0x021b001c 0x0200803A	// MMDC0_MDSCR, MR2 write, CS1
+//DATA 4	0x021b001c 0x0000803B	// MMDC0_MDSCR, MR3 write, CS1
+//DATA 4	0x021b001c 0x00048039	// MMDC0_MDSCR, MR1 write, CS1
+//DATA 4	0x021b001c 0x15208038	// MMDC0_MDSCR, MR0write, CS1
+//DATA 4	0x021b001c 0x04008048	// MMDC0_MDSCR, ZQ calibration command sent to device on CS1
+			
+DATA 4	0x021b0020 0x00007800	// MMDC0_MDREF
+			
+DATA 4	0x021b0818 0x00022227	// DDR_PHY_P0_MPODTCTRL
+DATA 4	0x021b4818 0x00022227	// DDR_PHY_P1_MPODTCTRL
+			
+DATA 4	0x021b0004 0x0002556D	// MMDC0_MDPDC now SDCTL power down enabled
+			
+DATA 4	0x021b0404 0x00011006	// MMDC0_MAPSR ADOPT power down enabled, MMDC will enter automatically to self-refresh while the number of idle cycle reached.
+			
+DATA 4	0x021b001c 0x00000000	// MMDC0_MDSCR, clear this register (especially the configuration bit as initialization is complete)
\ No newline at end of file
diff --git a/board/isee/igep0046/mx6q_igep0046_4x512_nt.cfg b/board/isee/igep0046/mx6q_igep0046_4x512_nt.cfg
index dd10a58..926c1d5 100644
--- a/board/isee/igep0046/mx6q_igep0046_4x512_nt.cfg
+++ b/board/isee/igep0046/mx6q_igep0046_4x512_nt.cfg
@@ -1,142 +1,142 @@
-/*

- * Copyright (C) 2016 ISEE 2007 SL - http://www.isee.biz

- *

- * SPDX-License-Identifier:	GPL-2.0+

- *

- * Refer docs/README.imxmage for more details about how-to configure

- * and create imximage boot image

- *

- * The syntax is taken as close as possible with the kwbimage

- */

-

-/* image version */

-

-IMAGE_VERSION 2

-

-/*

- * Boot Device : one of

- * spi, sd (the board has no nand neither onenand)

- */

-

-BOOT_FROM	sd

-

-/*

- * Device Configuration Data (DCD)

- *

- * Each entry must have the format:

- * Addr-type           Address        Value

- *

- * where:

- *	Addr-type register length (1,2 or 4 bytes)

- *	Address	  absolute address of the register

- *	value	  value to be stored in the register

- */

-DATA 4, 0x020e0798, 0x000C0000

-DATA 4, 0x020e0758, 0x00000000

-DATA 4, 0x020e0588, 0x00020030

-DATA 4, 0x020e0594, 0x00020030

-DATA 4, 0x020e056c, 0x00020030

-DATA 4, 0x020e0578, 0x00020030

-DATA 4, 0x020e074c, 0x00000030

-DATA 4, 0x020e057c, 0x00020030

-DATA 4, 0x020e058c, 0x00000000

-DATA 4, 0x020e059c, 0x00003030

-DATA 4, 0x020e05a0, 0x00003030

-DATA 4, 0x020e078c, 0x00000030

-DATA 4, 0x020e0750, 0x00020000

-DATA 4, 0x020e05a8, 0x00000030

-DATA 4, 0x020e05b0, 0x00000030

-DATA 4, 0x020e0524, 0x00000030

-DATA 4, 0x020e051c, 0x00000030

-DATA 4, 0x020e0518, 0x00000030

-DATA 4, 0x020e050c, 0x00000030

-DATA 4, 0x020e05b8, 0x00000030

-DATA 4, 0x020e05c0, 0x00000030

-DATA 4, 0x020e0774, 0x00020000

-DATA 4, 0x020e0784, 0x00000030

-DATA 4, 0x020e0788, 0x00000030

-DATA 4, 0x020e0794, 0x00000030

-DATA 4, 0x020e079c, 0x00000030

-DATA 4, 0x020e07a0, 0x00000030

-DATA 4, 0x020e07a4, 0x00000030

-DATA 4, 0x020e07a8, 0x00000030

-DATA 4, 0x020e0748, 0x00000030

-DATA 4, 0x020e05ac, 0x00020030

-DATA 4, 0x020e05b4, 0x00020030

-DATA 4, 0x020e0528, 0x00020030

-DATA 4, 0x020e0520, 0x00020030

-DATA 4, 0x020e0514, 0x00020030

-DATA 4, 0x020e0510, 0x00020030

-DATA 4, 0x020e05bc, 0x00020030

-DATA 4, 0x020e05c4, 0x00020030

-DATA 4, 0x021b0800, 0xa1390003

-DATA 4, 0x021b080c, 0x001F001F

-DATA 4, 0x021b0810, 0x001F001F

-DATA 4, 0x021b480c, 0x001F001F

-DATA 4, 0x021b4810, 0x001F001F

-DATA 4, 0x021b083c, 0x43270338

-DATA 4, 0x021b0840, 0x03200314

-DATA 4, 0x021b483c, 0x431A032F

-DATA 4, 0x021b4840, 0x03200263

-DATA 4, 0x021b0848, 0x4B434748

-DATA 4, 0x021b4848, 0x4445404C

-DATA 4, 0x021b0850, 0x38444542

-DATA 4, 0x021b4850, 0x4935493A

-DATA 4, 0x021b081c, 0x33333333

-DATA 4, 0x021b0820, 0x33333333

-DATA 4, 0x021b0824, 0x33333333

-DATA 4, 0x021b0828, 0x33333333

-DATA 4, 0x021b481c, 0x33333333

-DATA 4, 0x021b4820, 0x33333333

-DATA 4, 0x021b4824, 0x33333333

-DATA 4, 0x021b4828, 0x33333333

-DATA 4, 0x021b08b8, 0x00000800

-DATA 4, 0x021b48b8, 0x00000800

-DATA 4, 0x021b0004, 0x00020036

-DATA 4, 0x021b0008, 0x09444040

-DATA 4, 0x021b000c, 0x898E7974

-DATA 4, 0x021b0010, 0xDB538F64

-DATA 4, 0x021b0014, 0x01FF00DB

-DATA 4, 0x021b0018, 0x00081740

-DATA 4, 0x021b001c, 0x00008000

-DATA 4, 0x021b002c, 0x000026d2

-DATA 4, 0x021b0030, 0x008E1023

-DATA 4, 0x021b0040, 0x00000047

-DATA 4, 0x021b0000, 0x841A0000

-DATA 4, 0x021b001c, 0x04088032

-DATA 4, 0x021b001c, 0x00008033

-DATA 4, 0x021b001c, 0x00428031

-DATA 4, 0x021b001c, 0x19308030

-DATA 4, 0x021b001c, 0x04008040

-DATA 4, 0x021b0020, 0x00007800

-DATA 4, 0x021b0818, 0x00022227

-DATA 4, 0x021b4818, 0x00022227

-DATA 4, 0x021b0004, 0x00025576

-DATA 4, 0x021b0404, 0x00011006

-DATA 4, 0x021b001c, 0x00000000

-

-/* set the default clock gate to save power */

-DATA 4, 0x020c4068, 0x00C03F3F

-DATA 4, 0x020c406c, 0x0030FC03

-DATA 4, 0x020c4070, 0x0FFFC000

-DATA 4, 0x020c4074, 0x3FF00000

-DATA 4, 0x020c4078, 0x00FFF300

-DATA 4, 0x020c407c, 0x0F0000F3

-DATA 4, 0x020c4080, 0x000003FF

-

-/* enable AXI cache for VDOA/VPU/IPU */

-DATA 4, 0x020e0010, 0xF00000CF

-/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */

-DATA 4, 0x020e0018, 0x007F007F

-DATA 4, 0x020e001c, 0x007F007F

-

-/*

- * Setup CCM_CCOSR register as follows:

- *

- * cko1_en  = 1	   --> CKO1 enabled

- * cko1_div = 111  --> divide by 8

- * cko1_sel = 1011 --> ahb_clk_root

- *

- * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz

- */

-DATA 4, 0x020c4060, 0x000000fb

+/*
+ * Copyright (C) 2016 ISEE 2007 SL - http://www.isee.biz
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+/* image version */
+
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi, sd (the board has no nand neither onenand)
+ */
+
+BOOT_FROM	sd
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type           Address        Value
+ *
+ * where:
+ *	Addr-type register length (1,2 or 4 bytes)
+ *	Address	  absolute address of the register
+ *	value	  value to be stored in the register
+ */
+DATA 4, 0x020e0798, 0x000C0000
+DATA 4, 0x020e0758, 0x00000000
+DATA 4, 0x020e0588, 0x00020030
+DATA 4, 0x020e0594, 0x00020030
+DATA 4, 0x020e056c, 0x00020030
+DATA 4, 0x020e0578, 0x00020030
+DATA 4, 0x020e074c, 0x00000030
+DATA 4, 0x020e057c, 0x00020030
+DATA 4, 0x020e058c, 0x00000000
+DATA 4, 0x020e059c, 0x00003030
+DATA 4, 0x020e05a0, 0x00003030
+DATA 4, 0x020e078c, 0x00000030
+DATA 4, 0x020e0750, 0x00020000
+DATA 4, 0x020e05a8, 0x00000030
+DATA 4, 0x020e05b0, 0x00000030
+DATA 4, 0x020e0524, 0x00000030
+DATA 4, 0x020e051c, 0x00000030
+DATA 4, 0x020e0518, 0x00000030
+DATA 4, 0x020e050c, 0x00000030
+DATA 4, 0x020e05b8, 0x00000030
+DATA 4, 0x020e05c0, 0x00000030
+DATA 4, 0x020e0774, 0x00020000
+DATA 4, 0x020e0784, 0x00000030
+DATA 4, 0x020e0788, 0x00000030
+DATA 4, 0x020e0794, 0x00000030
+DATA 4, 0x020e079c, 0x00000030
+DATA 4, 0x020e07a0, 0x00000030
+DATA 4, 0x020e07a4, 0x00000030
+DATA 4, 0x020e07a8, 0x00000030
+DATA 4, 0x020e0748, 0x00000030
+DATA 4, 0x020e05ac, 0x00020030
+DATA 4, 0x020e05b4, 0x00020030
+DATA 4, 0x020e0528, 0x00020030
+DATA 4, 0x020e0520, 0x00020030
+DATA 4, 0x020e0514, 0x00020030
+DATA 4, 0x020e0510, 0x00020030
+DATA 4, 0x020e05bc, 0x00020030
+DATA 4, 0x020e05c4, 0x00020030
+DATA 4, 0x021b0800, 0xa1390003
+DATA 4, 0x021b080c, 0x001F001F
+DATA 4, 0x021b0810, 0x001F001F
+DATA 4, 0x021b480c, 0x001F001F
+DATA 4, 0x021b4810, 0x001F001F
+DATA 4, 0x021b083c, 0x43270338
+DATA 4, 0x021b0840, 0x03200314
+DATA 4, 0x021b483c, 0x431A032F
+DATA 4, 0x021b4840, 0x03200263
+DATA 4, 0x021b0848, 0x4B434748
+DATA 4, 0x021b4848, 0x4445404C
+DATA 4, 0x021b0850, 0x38444542
+DATA 4, 0x021b4850, 0x4935493A
+DATA 4, 0x021b081c, 0x33333333
+DATA 4, 0x021b0820, 0x33333333
+DATA 4, 0x021b0824, 0x33333333
+DATA 4, 0x021b0828, 0x33333333
+DATA 4, 0x021b481c, 0x33333333
+DATA 4, 0x021b4820, 0x33333333
+DATA 4, 0x021b4824, 0x33333333
+DATA 4, 0x021b4828, 0x33333333
+DATA 4, 0x021b08b8, 0x00000800
+DATA 4, 0x021b48b8, 0x00000800
+DATA 4, 0x021b0004, 0x00020036
+DATA 4, 0x021b0008, 0x09444040
+DATA 4, 0x021b000c, 0x898E7974
+DATA 4, 0x021b0010, 0xDB538F64
+DATA 4, 0x021b0014, 0x01FF00DB
+DATA 4, 0x021b0018, 0x00081740
+DATA 4, 0x021b001c, 0x00008000
+DATA 4, 0x021b002c, 0x000026d2
+DATA 4, 0x021b0030, 0x008E1023
+DATA 4, 0x021b0040, 0x00000047
+DATA 4, 0x021b0000, 0x841A0000
+DATA 4, 0x021b001c, 0x04088032
+DATA 4, 0x021b001c, 0x00008033
+DATA 4, 0x021b001c, 0x00428031
+DATA 4, 0x021b001c, 0x19308030
+DATA 4, 0x021b001c, 0x04008040
+DATA 4, 0x021b0020, 0x00007800
+DATA 4, 0x021b0818, 0x00022227
+DATA 4, 0x021b4818, 0x00022227
+DATA 4, 0x021b0004, 0x00025576
+DATA 4, 0x021b0404, 0x00011006
+DATA 4, 0x021b001c, 0x00000000
+
+/* set the default clock gate to save power */
+DATA 4, 0x020c4068, 0x00C03F3F
+DATA 4, 0x020c406c, 0x0030FC03
+DATA 4, 0x020c4070, 0x0FFFC000
+DATA 4, 0x020c4074, 0x3FF00000
+DATA 4, 0x020c4078, 0x00FFF300
+DATA 4, 0x020c407c, 0x0F0000F3
+DATA 4, 0x020c4080, 0x000003FF
+
+/* enable AXI cache for VDOA/VPU/IPU */
+DATA 4, 0x020e0010, 0xF00000CF
+/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
+DATA 4, 0x020e0018, 0x007F007F
+DATA 4, 0x020e001c, 0x007F007F
+
+/*
+ * Setup CCM_CCOSR register as follows:
+ *
+ * cko1_en  = 1	   --> CKO1 enabled
+ * cko1_div = 111  --> divide by 8
+ * cko1_sel = 1011 --> ahb_clk_root
+ *
+ * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz
+ */
+DATA 4, 0x020c4060, 0x000000fb
\ No newline at end of file
diff --git a/board/isee/igep0046/pfuze.c b/board/isee/igep0046/pfuze.c
index d6a209e..e3aa89f 100644
--- a/board/isee/igep0046/pfuze.c
+++ b/board/isee/igep0046/pfuze.c
@@ -89,4 +89,4 @@ struct pmic *pfuze_common_init(unsigned char i2cbus)
 	pmic_reg_write(p, PFUZE100_SW1CCONF, reg);
 
 	return p;
-}
+}
\ No newline at end of file
diff --git a/board/isee/igep0046/pfuze.h b/board/isee/igep0046/pfuze.h
index 53cfc99..131c7cc 100644
--- a/board/isee/igep0046/pfuze.h
+++ b/board/isee/igep0046/pfuze.h
@@ -10,4 +10,4 @@
 struct pmic *pfuze_common_init(unsigned char i2cbus);
 int pfuze_mode_init(struct pmic *p, u32 mode);
 
-#endif
+#endif
\ No newline at end of file