diff options
| author | Javier Martinez Canillas <javier@dowhile0.org> | 2012-07-28 01:19:34 +0000 |
|---|---|---|
| committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2012-09-01 14:58:11 +0200 |
| commit | d271a6114177ca9c80cc9676773f49a050e13381 (patch) | |
| tree | 1946f60724fbe0e4d55b37cba3b26b8cab77adb2 /board/isee/igep0030/igep0030.c | |
| parent | 41708a5db4e88208908fb17bffcd9447953806f8 (diff) | |
| download | u-boot-imx-d271a6114177ca9c80cc9676773f49a050e13381.zip u-boot-imx-d271a6114177ca9c80cc9676773f49a050e13381.tar.gz u-boot-imx-d271a6114177ca9c80cc9676773f49a050e13381.tar.bz2 | |
OMAP3: igep00x0: add SPL support for IGEP-based boards
This patch adds SPL support for IGEP-based boards.
Tested on an IGEPv2 Rev.C board with Micron NAND Flash memory.
Signed-off-by: Javier Martinez Canillas <javier@dowhile0.org>
Diffstat (limited to 'board/isee/igep0030/igep0030.c')
| -rw-r--r-- | board/isee/igep0030/igep0030.c | 42 |
1 files changed, 41 insertions, 1 deletions
diff --git a/board/isee/igep0030/igep0030.c b/board/isee/igep0030/igep0030.c index 653c1b5..4f8b645 100644 --- a/board/isee/igep0030/igep0030.c +++ b/board/isee/igep0030/igep0030.c @@ -45,7 +45,47 @@ int board_init(void) return 0; } -#ifdef CONFIG_GENERIC_MMC +#ifdef CONFIG_SPL_BUILD +/* + * Routine: omap_rev_string + * Description: For SPL builds output board rev + */ +void omap_rev_string(void) +{ +} + +/* + * Routine: get_board_mem_timings + * Description: If we use SPL then there is no x-loader nor config header + * so we have to setup the DDR timings ourself on both banks. + */ +void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl, + u32 *mr) +{ + *mr = MICRON_V_MR_165; +#ifdef CONFIG_BOOT_NAND + *mcfg = MICRON_V_MCFG_200(512 << 20); + *ctrla = MICRON_V_ACTIMA_200; + *ctrlb = MICRON_V_ACTIMB_200; + *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; +#else + if (get_cpu_family() == CPU_OMAP34XX) { + *mcfg = NUMONYX_V_MCFG_165(512 << 20); + *ctrla = NUMONYX_V_ACTIMA_165; + *ctrlb = NUMONYX_V_ACTIMB_165; + *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; + + } else { + *mcfg = NUMONYX_V_MCFG_200(512 << 20); + *ctrla = NUMONYX_V_ACTIMA_200; + *ctrlb = NUMONYX_V_ACTIMB_200; + *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; + } +#endif +} +#endif + +#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD) int board_mmc_init(bd_t *bis) { omap_mmc_init(0, 0, 0); |