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authorYe.Li <B37916@freescale.com>2015-03-27 17:17:14 +0800
committerPeng Fan <Peng.Fan@freescale.com>2015-04-29 15:04:25 +0800
commit3e0d4789c80b1809f5fbd425cda8fac621c2dcb1 (patch)
tree6038740f6d7d225811436282c77ed7881218a784 /board/intercontrol/digsy_mtc/eeprom.h
parent45f27956f3e6cc7a254e91137111843c91710d60 (diff)
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MLK-10492-1 imx: mx7d: Update LCDIF clock settings
To support lower clock frequency, needs to set post divider and test divider in PLL_VIDEO. So update LCDIF clock settings function to support this feature. Signed-off-by: Ye.Li <B37916@freescale.com> (cherry picked from commit b4d3b2a8eaf1ad1dc529ae2348d1646a2833b701)
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