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authorBin Meng <bmeng.cn@gmail.com>2014-12-17 15:50:38 +0800
committerSimon Glass <sjg@chromium.org>2014-12-18 17:26:06 -0700
commitb71eec3129c2626bfb1e98141b317d958e3cf384 (patch)
tree960f136fd30d146892608b46f8eeff49c90c6f25 /board/intel
parent0f61de8d9dba4ebfc4ea4b2da7f91adc937b3875 (diff)
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x86: ich6-gpio: Add Intel Tunnel Creek GPIO support
Intel Tunnel Creek GPIO register block is compatible with current ich6-gpio driver, except the offset and content of GPIO block base address register in the LPC PCI configuration space are different. Use u16 instead of u32 to store the 16-bit I/O address of the GPIO registers so that it could support both Ivybridge and Tunnel Creek. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'board/intel')
-rw-r--r--board/intel/crownbay/crownbay.c5
1 files changed, 5 insertions, 0 deletions
diff --git a/board/intel/crownbay/crownbay.c b/board/intel/crownbay/crownbay.c
index 8c6df98..54670d3 100644
--- a/board/intel/crownbay/crownbay.c
+++ b/board/intel/crownbay/crownbay.c
@@ -19,3 +19,8 @@ int board_early_init_f(void)
return 0;
}
+
+void setup_pch_gpios(u16 gpiobase, const struct pch_gpio_map *gpio)
+{
+ return;
+}