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author | Marian Balakowicz <m8@semihalf.com> | 2007-11-15 13:29:55 +0100 |
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committer | Marian Balakowicz <m8@semihalf.com> | 2007-11-15 13:29:55 +0100 |
commit | 5fb6d7191e206cdde0e23140fd8111caed93a595 (patch) | |
tree | 957d4bec905f329c786ff5d3785462a527576e72 /board/inka4x0/mt48lc16m16a2-75.h | |
parent | f23cb34c367bb27585a4fdb8a75277370e7d0596 (diff) | |
download | u-boot-imx-5fb6d7191e206cdde0e23140fd8111caed93a595.zip u-boot-imx-5fb6d7191e206cdde0e23140fd8111caed93a595.tar.gz u-boot-imx-5fb6d7191e206cdde0e23140fd8111caed93a595.tar.bz2 |
[INKA4x0] NG hardware: SDRAM support
Add support for three new DDR chips that may be present on a NG
INKA4x0 hardware: HYB25D512160BF-5, K4H511638C-7CB3, T46V32M16BN-6IT.
Cleanup board/inka4x0/mt48lc16m16a2-75.h file.
Signed-off-by: Marian Balakowicz <m8@semihalf.com>
Diffstat (limited to 'board/inka4x0/mt48lc16m16a2-75.h')
-rw-r--r-- | board/inka4x0/mt48lc16m16a2-75.h | 19 |
1 files changed, 1 insertions, 18 deletions
diff --git a/board/inka4x0/mt48lc16m16a2-75.h b/board/inka4x0/mt48lc16m16a2-75.h index 13a97ac..1547725 100644 --- a/board/inka4x0/mt48lc16m16a2-75.h +++ b/board/inka4x0/mt48lc16m16a2-75.h @@ -21,27 +21,10 @@ * MA 02111-1307 USA */ -#define SDRAM_DDR 1 /* is SDR */ +#define SDRAM_DDR 0 /* is SDR */ -#if defined(CONFIG_MPC5200) /* Settings for XLB = 132 MHz */ #define SDRAM_MODE 0x00CD0000 -/* #define SDRAM_MODE 0x008D0000 */ /* CAS latency 2 */ #define SDRAM_CONTROL 0x504F0000 #define SDRAM_CONFIG1 0xD2322800 -/* #define SDRAM_CONFIG1 0xD2222800 */ /* CAS latency 2 */ -/*#define SDRAM_CONFIG1 0xD7322800 */ /* SDRAM controller bug workaround */ #define SDRAM_CONFIG2 0x8AD70000 -/*#define SDRAM_CONFIG2 0xDDD70000 */ /* SDRAM controller bug workaround */ - -#elif defined(CONFIG_MGT5100) -/* Settings for XLB = 66 MHz */ -#define SDRAM_MODE 0x008D0000 -#define SDRAM_CONTROL 0x504F0000 -#define SDRAM_CONFIG1 0xC2222600 -#define SDRAM_CONFIG2 0x88B70004 -#define SDRAM_ADDRSEL 0x02000000 - -#else -#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined -#endif |