diff options
| author | Marian Balakowicz <m8@semihalf.com> | 2007-11-15 13:29:55 +0100 |
|---|---|---|
| committer | Marian Balakowicz <m8@semihalf.com> | 2007-11-15 13:29:55 +0100 |
| commit | 5fb6d7191e206cdde0e23140fd8111caed93a595 (patch) | |
| tree | 957d4bec905f329c786ff5d3785462a527576e72 /board/inka4x0/mt46v32m16-75.h | |
| parent | f23cb34c367bb27585a4fdb8a75277370e7d0596 (diff) | |
| download | u-boot-imx-5fb6d7191e206cdde0e23140fd8111caed93a595.zip u-boot-imx-5fb6d7191e206cdde0e23140fd8111caed93a595.tar.gz u-boot-imx-5fb6d7191e206cdde0e23140fd8111caed93a595.tar.bz2 | |
[INKA4x0] NG hardware: SDRAM support
Add support for three new DDR chips that may be present on a NG
INKA4x0 hardware: HYB25D512160BF-5, K4H511638C-7CB3, T46V32M16BN-6IT.
Cleanup board/inka4x0/mt48lc16m16a2-75.h file.
Signed-off-by: Marian Balakowicz <m8@semihalf.com>
Diffstat (limited to 'board/inka4x0/mt46v32m16-75.h')
| -rw-r--r-- | board/inka4x0/mt46v32m16-75.h | 32 |
1 files changed, 32 insertions, 0 deletions
diff --git a/board/inka4x0/mt46v32m16-75.h b/board/inka4x0/mt46v32m16-75.h new file mode 100644 index 0000000..7eb1f50 --- /dev/null +++ b/board/inka4x0/mt46v32m16-75.h @@ -0,0 +1,32 @@ +/* + * Copyright (C) 2007 Semihalf + * Written by Marian Balakowicz <m8@semihalf.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#define SDRAM_DDR 1 /* is DDR */ + +/* Settings for XLB = 132 MHz */ +#define SDRAM_MODE 0x018D0000 +#define SDRAM_EMODE 0x40090000 +#define SDRAM_CONTROL 0x714F0F00 +#define SDRAM_CONFIG1 0x73711930 +#define SDRAM_CONFIG2 0x46770000 +#define SDRAM_TAPDELAY 0x10000000 |