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| author | Grant Erickson <gerickson@nuovations.com> | 2008-07-09 11:55:46 -0700 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2008-07-11 13:18:12 +0200 |
| commit | 5b457d00730d4aa0c6450d21a9104723e606fb98 (patch) | |
| tree | 3f89dc42f698f5f891a3fba0d712fc705b61c2c3 /board/incaip | |
| parent | 0ce5c8675bb2c61f1d71fb97f0bbe822663fb93d (diff) | |
| download | u-boot-imx-5b457d00730d4aa0c6450d21a9104723e606fb98.zip u-boot-imx-5b457d00730d4aa0c6450d21a9104723e606fb98.tar.gz u-boot-imx-5b457d00730d4aa0c6450d21a9104723e606fb98.tar.bz2 | |
PPC4xx: Correct SDRAM_MCSTAT for PPC405EX(r)
While the PowerPC 405EX(r) shares in common the AMCC/IBM DDR2 SDRAM
controller core also used in the 440SP, 440SPe, 460EX, and 460GT, in
the 405EX(r), SDRAM_MCSTAT has a different DCR value.
Its present value on the 405EX(r) causes a read back of 0xFFFFFFFF
which causes SDRAM initialization to periodically fail since it can
prematurely indicate SDRAM ready status.
Signed-off-by: Grant Erickson <gerickson@nuovations.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'board/incaip')
0 files changed, 0 insertions, 0 deletions