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| author | Paul Burton <paul.burton@imgtec.com> | 2013-11-26 17:45:27 +0000 |
|---|---|---|
| committer | Daniel Schwierzeck <daniel.schwierzeck@gmail.com> | 2013-11-26 21:49:34 +0100 |
| commit | bea12b782337105feeb3aeb0875d110eed007803 (patch) | |
| tree | f2f850e5ab8953d093ca212d7f5f8f02083133ac /board/imgtec | |
| parent | 72117dadcbbdffda447daa1e26b4cc4007f61160 (diff) | |
| download | u-boot-imx-bea12b782337105feeb3aeb0875d110eed007803.zip u-boot-imx-bea12b782337105feeb3aeb0875d110eed007803.tar.gz u-boot-imx-bea12b782337105feeb3aeb0875d110eed007803.tar.bz2 | |
malta: enable PIIX4 SERIRQ
Whilst U-boot does not require this itself, Linux currently relies upon
it having been muxed and enabled by the bootloader. Thus in order to
preserve compatibility with current kernels before a fix is merged in
Linux we will enable the SERIRQ interrupt and mux it to its pin.
Without doing this current kernels will never receive serial port
interrupts and the end result is typically that userland appears to
hang.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Diffstat (limited to 'board/imgtec')
| -rw-r--r-- | board/imgtec/malta/malta.c | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/board/imgtec/malta/malta.c b/board/imgtec/malta/malta.c index a1a4c01..d363e49 100644 --- a/board/imgtec/malta/malta.c +++ b/board/imgtec/malta/malta.c @@ -171,6 +171,8 @@ struct serial_device *default_serial_console(void) void pci_init_board(void) { pci_dev_t bdf; + u32 val32; + u8 val8; switch (malta_sys_con()) { case SYSCON_GT64120: @@ -205,4 +207,14 @@ void pci_init_board(void) pci_write_config_byte(bdf, PCI_CFG_PIIX4_PIRQRCB, 10); pci_write_config_byte(bdf, PCI_CFG_PIIX4_PIRQRCC, 11); pci_write_config_byte(bdf, PCI_CFG_PIIX4_PIRQRCD, 11); + + /* mux SERIRQ onto SERIRQ pin */ + pci_read_config_dword(bdf, PCI_CFG_PIIX4_GENCFG, &val32); + val32 |= PCI_CFG_PIIX4_GENCFG_SERIRQ; + pci_write_config_dword(bdf, PCI_CFG_PIIX4_GENCFG, val32); + + /* enable SERIRQ - Linux currently depends upon this */ + pci_read_config_byte(bdf, PCI_CFG_PIIX4_SERIRQC, &val8); + val8 |= PCI_CFG_PIIX4_SERIRQC_EN | PCI_CFG_PIIX4_SERIRQC_CONT; + pci_write_config_byte(bdf, PCI_CFG_PIIX4_SERIRQC, val8); } |