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| author | Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> | 2008-10-16 15:01:15 +0200 |
|---|---|---|
| committer | Wolfgang Denk <wd@denx.de> | 2008-10-18 21:54:03 +0200 |
| commit | 6d0f6bcf337c5261c08fabe12982178c2c489d76 (patch) | |
| tree | ae13958ffa9c6b58c2ea97aac07a4ad2f04a350f /board/idmr/idmr.c | |
| parent | 71edc271816ec82cf0550dd6980be2da3cc2ad9e (diff) | |
| download | u-boot-imx-6d0f6bcf337c5261c08fabe12982178c2c489d76.zip u-boot-imx-6d0f6bcf337c5261c08fabe12982178c2c489d76.tar.gz u-boot-imx-6d0f6bcf337c5261c08fabe12982178c2c489d76.tar.bz2 | |
rename CFG_ macros to CONFIG_SYS
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Diffstat (limited to 'board/idmr/idmr.c')
| -rw-r--r-- | board/idmr/idmr.c | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/board/idmr/idmr.c b/board/idmr/idmr.c index 4f073fc..3771c19 100644 --- a/board/idmr/idmr.c +++ b/board/idmr/idmr.c @@ -35,7 +35,7 @@ phys_size_t initdram (int board_type) { /* * After reset, CS0 is configured to cover entire address space. We * need to configure it to its proper values, so that writes to - * CFG_SDRAM_BASE and vicinity during SDRAM controller setup below do + * CONFIG_SYS_SDRAM_BASE and vicinity during SDRAM controller setup below do * now fall under CS0 (see 16.3.1 of the MCF5271 Reference Manual). */ @@ -99,7 +99,7 @@ phys_size_t initdram (int board_type) { * PS: 16 bit */ mbar_writeLong(MCF_SDRAMC_DACR0, - MCF_SDRAMC_DACRn_BA(CFG_SDRAM_BASE>>18) | + MCF_SDRAMC_DACRn_BA(CONFIG_SYS_SDRAM_BASE>>18) | MCF_SDRAMC_DACRn_BA(0x00) | MCF_SDRAMC_DACRn_CASL(0x03) | MCF_SDRAMC_DACRn_CBM(0x03) | @@ -117,7 +117,7 @@ phys_size_t initdram (int board_type) { MCF_SDRAMC_DACRn_IP); /* Write to this block to initiate precharge */ - *(volatile u16 *)(CFG_SDRAM_BASE) = 0xa5a5; + *(volatile u16 *)(CONFIG_SYS_SDRAM_BASE) = 0xa5a5; /* * Wait at least 20ns to allow banks to precharge (t_RP = 20ns). We @@ -153,9 +153,9 @@ phys_size_t initdram (int board_type) { * Burst Type = Sequential * Burst Length = 1 */ - *(volatile u32 *)(CFG_SDRAM_BASE + 0x1800) = 0xa5a5a5a5; + *(volatile u32 *)(CONFIG_SYS_SDRAM_BASE + 0x1800) = 0xa5a5a5a5; - return CFG_SDRAM_SIZE * 1024 * 1024; + return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; }; |