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| author | Dirk Eibach <eibach@gdsys.de> | 2011-04-06 13:53:46 +0200 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2011-04-21 10:34:41 +0200 |
| commit | 5cb4100f5825de5181be1edce8a020bf646a9475 (patch) | |
| tree | 7e08c3969bcb47430a96ee6da75080484b68186e /board/gdsys | |
| parent | 8aa50540e4e8fe599857db522d58a55469bbb254 (diff) | |
| download | u-boot-imx-5cb4100f5825de5181be1edce8a020bf646a9475.zip u-boot-imx-5cb4100f5825de5181be1edce8a020bf646a9475.tar.gz u-boot-imx-5cb4100f5825de5181be1edce8a020bf646a9475.tar.bz2 | |
ppc4xx: Adapt DLVision 10G to new FPGA firmware
Signed-off-by: Dirk Eibach <eibach@gdsys.de>
Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'board/gdsys')
| -rw-r--r-- | board/gdsys/405ep/405ep.c | 9 | ||||
| -rw-r--r-- | board/gdsys/405ep/dlvision-10g.c | 25 |
2 files changed, 28 insertions, 6 deletions
diff --git a/board/gdsys/405ep/405ep.c b/board/gdsys/405ep/405ep.c index 86a3ec8..8b80533 100644 --- a/board/gdsys/405ep/405ep.c +++ b/board/gdsys/405ep/405ep.c @@ -110,6 +110,11 @@ int board_early_init_f(void) for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) { ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(k); +#ifdef CONFIG_SYS_FPGA_NO_RFL_HI + u16 *reflection_target = &fpga->reflection_low; +#else + u16 *reflection_target = &fpga->reflection_high; +#endif /* * wait for fpga out of reset */ @@ -117,9 +122,11 @@ int board_early_init_f(void) while (1) { out_le16(&fpga->reflection_low, REFLECTION_TESTPATTERN); - if (in_le16(&fpga->reflection_high) == + + if (in_le16(reflection_target) == REFLECTION_TESTPATTERN_INV) break; + udelay(100000); if (ctr++ > 5) { gd->fpga_state[k] |= diff --git a/board/gdsys/405ep/dlvision-10g.c b/board/gdsys/405ep/dlvision-10g.c index d7b4fb2..0388541 100644 --- a/board/gdsys/405ep/dlvision-10g.c +++ b/board/gdsys/405ep/dlvision-10g.c @@ -34,6 +34,8 @@ #define LATCH2_BASE (CONFIG_SYS_LATCH_BASE + 0x200) #define LATCH2_MC2_PRESENT_N 0x0080 +#define LATCH3_BASE (CONFIG_SYS_LATCH_BASE + 0x300) + enum { UNITTYPE_VIDEO_USER = 0, UNITTYPE_MAIN_USER = 1, @@ -63,6 +65,20 @@ enum { RAM_DDR2_64 = 2, }; +static unsigned int get_hwver(void) +{ + u16 latch3 = in_le16((void *)LATCH3_BASE); + + return latch3 & 0x0003; +} + +static unsigned int get_mc2_present(void) +{ + u16 latch2 = in_le16((void *)LATCH2_BASE); + + return !(latch2 & LATCH2_MC2_PRESENT_N); +} + static void print_fpga_info(unsigned dev) { ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(dev); @@ -210,7 +226,6 @@ static void print_fpga_info(unsigned dev) int checkboard(void) { char *s = getenv("serial#"); - u16 latch2 = in_le16((void *)LATCH2_BASE); printf("Board: "); @@ -224,7 +239,7 @@ int checkboard(void) puts("\n"); print_fpga_info(0); - if (!(latch2 & LATCH2_MC2_PRESENT_N)) + if (get_mc2_present()) print_fpga_info(1); return 0; @@ -234,15 +249,15 @@ int last_stage_init(void) { ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(0); u16 versions = in_le16(&fpga->versions); - u16 latch2 = in_le16((void *)LATCH2_BASE); if (((versions >> 4) & 0x000f) != UNITTYPE_MAIN_USER) return 0; - if (!get_fpga_state(0)) + if (!get_fpga_state(0) || (get_hwver() == HWVER_101)) osd_probe(0); - if (!(latch2 & LATCH2_MC2_PRESENT_N) && !get_fpga_state(1)) + if (get_mc2_present() && + (!get_fpga_state(1) || (get_hwver() == HWVER_101))) osd_probe(1); return 0; |