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author | Dirk Eibach <eibach@gdsys.de> | 2013-06-26 15:55:17 +0200 |
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committer | Andy Fleming <afleming@freescale.com> | 2013-07-16 17:44:30 -0500 |
commit | b9944a77f909e343f930dcbcc597224e65dfcca9 (patch) | |
tree | 40dc13f48eb87abc3cadde6e96c91665239ff9d6 /board/gdsys/p1022/ddr.c | |
parent | b8eee4354f33b9810d929b6f7df74238b538e5a8 (diff) | |
download | u-boot-imx-b9944a77f909e343f930dcbcc597224e65dfcca9.zip u-boot-imx-b9944a77f909e343f930dcbcc597224e65dfcca9.tar.gz u-boot-imx-b9944a77f909e343f930dcbcc597224e65dfcca9.tar.bz2 |
mpc85xx: Add gdsys ControlCenter Digital board
The gdsys ControlCenter Digital board is based on a Freescale P1022 QorIQ SOC.
It boots from SPI-Flash but can be configured to boot from SD-card for
factory programming and testing.
On board peripherals include:
- 2x GbE
- Lattice ECP3 FPGA connected via PCIe
- mSATA RAID1
- USB host
- DisplayPort video output
- Atmel TPM
Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc>
Signed-off-by: Reinhard Pfau <reinhard.pfau@gdsys.cc>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Diffstat (limited to 'board/gdsys/p1022/ddr.c')
-rw-r--r-- | board/gdsys/p1022/ddr.c | 71 |
1 files changed, 71 insertions, 0 deletions
diff --git a/board/gdsys/p1022/ddr.c b/board/gdsys/p1022/ddr.c new file mode 100644 index 0000000..4a652de --- /dev/null +++ b/board/gdsys/p1022/ddr.c @@ -0,0 +1,71 @@ +/* + * Copyright 2010 Freescale Semiconductor, Inc. + * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com> + * Timur Tabi <timur@freescale.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the Free + * Software Foundation; either version 2 of the License, or (at your option) + * any later version. + */ + +#include <common.h> +#include <i2c.h> + +#include <asm/fsl_ddr_sdram.h> +#include <asm/fsl_ddr_dimm_params.h> + +void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm, + unsigned int ctrl_num) +{ + unsigned int i; + + if (ctrl_num) { + printf("Wrong parameter for controller number %d", ctrl_num); + return; + } + if (!pdimm->n_ranks) + return; + + /* set odt_rd_cfg and odt_wr_cfg. */ + for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { + popts->cs_local_opts[i].odt_rd_cfg = 0; + popts->cs_local_opts[i].odt_wr_cfg = 1; + } + + popts->clk_adjust = 5; + popts->cpo_override = 0x1f; + popts->write_data_delay = 2; + popts->half_strength_driver_enable = 1; + + /* Per AN4039, enable ZQ calibration. */ + popts->zq_en = 1; +} + +#ifdef CONFIG_SPD_EEPROM +/* + * we only have a "fake" SPD-EEPROM here, which has 16 bit addresses + */ +void get_spd(generic_spd_eeprom_t *spd, u8 i2c_address) +{ + int ret = i2c_read(i2c_address, 0, 2, (uchar *)spd, + sizeof(generic_spd_eeprom_t)); + + if (ret) { + if (i2c_address == +#ifdef SPD_EEPROM_ADDRESS + SPD_EEPROM_ADDRESS +#elif defined(SPD_EEPROM_ADDRESS1) + SPD_EEPROM_ADDRESS1 +#endif + ) { + printf("DDR: failed to read SPD from address %u\n", + i2c_address); + } else { + debug("DDR: failed to read SPD from address %u\n", + i2c_address); + } + memset(spd, 0, sizeof(generic_spd_eeprom_t)); + } +} +#endif |