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author | Dirk Eibach <dirk.eibach@gdsys.cc> | 2014-11-13 19:21:18 +0100 |
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committer | Stefan Roese <sr@denx.de> | 2014-11-19 08:48:42 +0100 |
commit | 50dcf89d90b3597d86f5d26f131eabc98bbd5209 (patch) | |
tree | 1625ea82bec2e9c51924f9dd3b761dff7b352b4b /board/gdsys/mpc8308/mpc8308.c | |
parent | a8cb9d0b17af9d7b3ad205cf83fbfd47528fa9d0 (diff) | |
download | u-boot-imx-50dcf89d90b3597d86f5d26f131eabc98bbd5209.zip u-boot-imx-50dcf89d90b3597d86f5d26f131eabc98bbd5209.tar.gz u-boot-imx-50dcf89d90b3597d86f5d26f131eabc98bbd5209.tar.bz2 |
mpc83xx: Add gdsys hrcon board
The gdsys hrcon board is based on a Freescale MPC8308 SOC.
It boots from NOR-Flash, kernel and rootfs are stored on
SD-Card.
On board peripherals include:
- 1x GbE (optional)
- Lattice ECP3 FPGA connected via eLBC and PCIe
Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc>
Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'board/gdsys/mpc8308/mpc8308.c')
-rw-r--r-- | board/gdsys/mpc8308/mpc8308.c | 109 |
1 files changed, 109 insertions, 0 deletions
diff --git a/board/gdsys/mpc8308/mpc8308.c b/board/gdsys/mpc8308/mpc8308.c new file mode 100644 index 0000000..4338a33 --- /dev/null +++ b/board/gdsys/mpc8308/mpc8308.c @@ -0,0 +1,109 @@ +/* + * (C) Copyright 2014 + * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <command.h> +#include <asm/processor.h> +#include <asm/io.h> +#include <asm/ppc4xx-gpio.h> +#include <asm/global_data.h> + +#include "mpc8308.h" +#include <gdsys_fpga.h> + +#define REFLECTION_TESTPATTERN 0xdede +#define REFLECTION_TESTPATTERN_INV (~REFLECTION_TESTPATTERN & 0xffff) + +#ifdef CONFIG_SYS_FPGA_NO_RFL_HI +#define REFLECTION_TESTREG reflection_low +#else +#define REFLECTION_TESTREG reflection_high +#endif + +DECLARE_GLOBAL_DATA_PTR; + +int get_fpga_state(unsigned dev) +{ + return gd->arch.fpga_state[dev]; +} + +void print_fpga_state(unsigned dev) +{ + if (gd->arch.fpga_state[dev] & FPGA_STATE_DONE_FAILED) + puts(" Waiting for FPGA-DONE timed out.\n"); + if (gd->arch.fpga_state[dev] & FPGA_STATE_REFLECTION_FAILED) + puts(" FPGA reflection test failed.\n"); +} + +int board_early_init_f(void) +{ + unsigned k; + + for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) + gd->arch.fpga_state[k] = 0; + + return 0; +} + +int board_early_init_r(void) +{ + unsigned k; + unsigned ctr; + + for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) + gd->arch.fpga_state[k] = 0; + + /* + * reset FPGA + */ + mpc8308_init(); + + mpc8308_set_fpga_reset(1); + + mpc8308_setup_hw(); + + for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) { + ctr = 0; + while (!mpc8308_get_fpga_done(k)) { + udelay(100000); + if (ctr++ > 5) { + gd->arch.fpga_state[k] |= + FPGA_STATE_DONE_FAILED; + break; + } + } + } + + udelay(10); + + mpc8308_set_fpga_reset(0); + + for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) { + /* + * wait for fpga out of reset + */ + ctr = 0; + while (1) { + u16 val; + + FPGA_SET_REG(k, reflection_low, REFLECTION_TESTPATTERN); + + FPGA_GET_REG(k, REFLECTION_TESTREG, &val); + if (val == REFLECTION_TESTPATTERN_INV) + break; + + udelay(100000); + if (ctr++ > 5) { + gd->arch.fpga_state[k] |= + FPGA_STATE_REFLECTION_FAILED; + break; + } + } + } + + return 0; +} |