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| author | Stefan Roese <sr@denx.de> | 2009-09-24 09:55:50 +0200 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2009-09-28 10:45:42 +0200 |
| commit | 952e7760bfc5b0e3b142b9ce34e7fbb7d008c900 (patch) | |
| tree | abd867c1a44dbc20bbd970c36c76f0355adc6df4 /board/gdsys/gdppc440etx/gdppc440etx.c | |
| parent | 984f10baac8ef6032df52f135943d6b0bc96f724 (diff) | |
| download | u-boot-imx-952e7760bfc5b0e3b142b9ce34e7fbb7d008c900.zip u-boot-imx-952e7760bfc5b0e3b142b9ce34e7fbb7d008c900.tar.gz u-boot-imx-952e7760bfc5b0e3b142b9ce34e7fbb7d008c900.tar.bz2 | |
ppc4xx: Convert PPC4xx UIC defines from lower case to upper case
The latest PPC4xx register cleanup patch missed the UIC defines.
This patch now changes lower case UIC defines to upper case.
Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'board/gdsys/gdppc440etx/gdppc440etx.c')
| -rw-r--r-- | board/gdsys/gdppc440etx/gdppc440etx.c | 30 |
1 files changed, 15 insertions, 15 deletions
diff --git a/board/gdsys/gdppc440etx/gdppc440etx.c b/board/gdsys/gdppc440etx/gdppc440etx.c index 27c159b..7cc1bf2 100644 --- a/board/gdsys/gdppc440etx/gdppc440etx.c +++ b/board/gdsys/gdppc440etx/gdppc440etx.c @@ -83,21 +83,21 @@ int board_early_init_f(void) /* * Setup the interrupt controller polarities, triggers, etc. */ - mtdcr(uic0sr, 0xffffffff); /* clear all */ - mtdcr(uic0er, 0x00000000); /* disable all */ - mtdcr(uic0cr, 0x00000009); /* ATI & UIC1 crit are critical */ - mtdcr(uic0pr, 0xfffffe13); /* per ref-board manual */ - mtdcr(uic0tr, 0x01c00008); /* per ref-board manual */ - mtdcr(uic0vr, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr(uic0sr, 0xffffffff); /* clear all */ - - mtdcr(uic1sr, 0xffffffff); /* clear all */ - mtdcr(uic1er, 0x00000000); /* disable all */ - mtdcr(uic1cr, 0x00000000); /* all non-critical */ - mtdcr(uic1pr, 0xffffe0ff); /* per ref-board manual */ - mtdcr(uic1tr, 0x00ffc000); /* per ref-board manual */ - mtdcr(uic1vr, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr(uic1sr, 0xffffffff); /* clear all */ + mtdcr(UIC0SR, 0xffffffff); /* clear all */ + mtdcr(UIC0ER, 0x00000000); /* disable all */ + mtdcr(UIC0CR, 0x00000009); /* ATI & UIC1 crit are critical */ + mtdcr(UIC0PR, 0xfffffe13); /* per ref-board manual */ + mtdcr(UIC0TR, 0x01c00008); /* per ref-board manual */ + mtdcr(UIC0VR, 0x00000001); /* int31 highest, base=0x000 */ + mtdcr(UIC0SR, 0xffffffff); /* clear all */ + + mtdcr(UIC1SR, 0xffffffff); /* clear all */ + mtdcr(UIC1ER, 0x00000000); /* disable all */ + mtdcr(UIC1CR, 0x00000000); /* all non-critical */ + mtdcr(UIC1PR, 0xffffe0ff); /* per ref-board manual */ + mtdcr(UIC1TR, 0x00ffc000); /* per ref-board manual */ + mtdcr(UIC1VR, 0x00000001); /* int31 highest, base=0x000 */ + mtdcr(UIC1SR, 0xffffffff); /* clear all */ /* * Setup other serial configuration |