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| author | Dirk Eibach <eibach@gdsys.de> | 2011-01-21 09:31:21 +0100 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2011-02-07 11:13:16 +0100 |
| commit | 2da0fc0d0fcdd991220cc120e5bc6d44991a5987 (patch) | |
| tree | c14838b5dbac4b29f646c72d0b460dd4c11dd83e /board/gdsys/405ep/iocon.c | |
| parent | 42d44f631c4e8e5359775bdc098f2fffde4e5c05 (diff) | |
| download | u-boot-imx-2da0fc0d0fcdd991220cc120e5bc6d44991a5987.zip u-boot-imx-2da0fc0d0fcdd991220cc120e5bc6d44991a5987.tar.gz u-boot-imx-2da0fc0d0fcdd991220cc120e5bc6d44991a5987.tar.bz2 | |
ppc4xx: Add DLVision-10G board support
Board support for the Guntermann & Drunck DLVision-10G.
Adds support for multiple FPGAs per board for gdsys 405ep
architecture.
Adds support for dual link osd hardware for gdsys 405ep.
Signed-off-by: Dirk Eibach <eibach@gdsys.de>
Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'board/gdsys/405ep/iocon.c')
| -rw-r--r-- | board/gdsys/405ep/iocon.c | 24 |
1 files changed, 10 insertions, 14 deletions
diff --git a/board/gdsys/405ep/iocon.c b/board/gdsys/405ep/iocon.c index ecd6cb2..20770e4 100644 --- a/board/gdsys/405ep/iocon.c +++ b/board/gdsys/405ep/iocon.c @@ -27,14 +27,9 @@ #include <asm/io.h> #include <asm/ppc4xx-gpio.h> -#include "../common/fpga.h" -#include "../common/osd.h" +#include <gdsys_fpga.h> -enum { - REG_VERSIONS = 0x0002, - REG_FPGA_VERSION = 0x0004, - REG_FPGA_FEATURES = 0x0006, -}; +#include "../common/osd.h" enum { UNITTYPE_MAIN_SERVER = 0, @@ -74,10 +69,11 @@ enum { */ int checkboard(void) { + ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(0); char *s = getenv("serial#"); - u16 versions = fpga_get_reg(REG_VERSIONS); - u16 fpga_version = fpga_get_reg(REG_FPGA_VERSION); - u16 fpga_features = fpga_get_reg(REG_FPGA_FEATURES); + u16 versions = in_le16(&fpga->versions); + u16 fpga_version = in_le16(&fpga->fpga_version); + u16 fpga_features = in_le16(&fpga->fpga_features); unsigned unit_type; unsigned hardware_version; unsigned feature_compression; @@ -214,7 +210,7 @@ int checkboard(void) int last_stage_init(void) { - return osd_probe(); + return osd_probe(0); } /* @@ -222,15 +218,15 @@ int last_stage_init(void) */ void fpga_gpio_set(int pin) { - out_le16((void *)(CONFIG_SYS_FPGA_BASE + 0x18), pin); + out_le16((void *)(CONFIG_SYS_FPGA0_BASE + 0x18), pin); } void fpga_gpio_clear(int pin) { - out_le16((void *)(CONFIG_SYS_FPGA_BASE + 0x16), pin); + out_le16((void *)(CONFIG_SYS_FPGA0_BASE + 0x16), pin); } int fpga_gpio_get(int pin) { - return in_le16((void *)(CONFIG_SYS_FPGA_BASE + 0x14)) & pin; + return in_le16((void *)(CONFIG_SYS_FPGA0_BASE + 0x14)) & pin; } |