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authorDirk Eibach <eibach@gdsys.de>2012-04-26 03:54:23 +0000
committerStefan Roese <sr@denx.de>2012-04-30 15:01:03 +0200
commitb19bf8344f2098bcc7746ef641c4c69f5aa7eb65 (patch)
tree3130d5892bd0b10bc9e8dbed269fe8de0d79b325 /board/gdsys/405ep/io.c
parent6e9e6c36a6a52562edb3e3b93cbad33f9dfe5585 (diff)
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powerpc/ppc4xx: Adapt gdsys 405ep boards to platform changes
Print fpga info at last_stage_init on gdsys 405ep boards. Use dtt_init() to startup fans. Signed-off-by: Dirk Eibach <eibach@gdsys.de> Cc: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'board/gdsys/405ep/io.c')
-rw-r--r--board/gdsys/405ep/io.c41
1 files changed, 28 insertions, 13 deletions
diff --git a/board/gdsys/405ep/io.c b/board/gdsys/405ep/io.c
index ac4cefd..85b61f1 100644
--- a/board/gdsys/405ep/io.c
+++ b/board/gdsys/405ep/io.c
@@ -27,6 +27,7 @@
#include <asm/io.h>
#include <asm/ppc4xx-gpio.h>
+#include <dtt.h>
#include <miiphy.h>
#include "405ep.h"
@@ -52,6 +53,14 @@ enum {
HWVER_122 = 3,
};
+int misc_init_r(void)
+{
+ /* startup fans */
+ dtt_init();
+
+ return 0;
+}
+
int configure_gbit_phy(unsigned char addr)
{
unsigned short value;
@@ -92,8 +101,22 @@ err_out:
*/
int checkboard(void)
{
- char buf[64];
- int i = getenv_f("serial#", buf, sizeof(buf));
+ char *s = getenv("serial#");
+
+ puts("Board: CATCenter Io");
+
+ if (s != NULL) {
+ puts(", serial# ");
+ puts(s);
+ }
+
+ puts("\n");
+
+ return 0;
+}
+
+static void print_fpga_info(void)
+{
ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(0);
u16 versions = in_le16(&fpga->versions);
u16 fpga_version = in_le16(&fpga->fpga_version);
@@ -108,15 +131,7 @@ int checkboard(void)
feature_channels = fpga_features & 0x007f;
feature_expansion = fpga_features & (1<<15);
- printf("Board: ");
-
- printf("CATCenter Io");
-
- if (i > 0) {
- puts(", serial# ");
- puts(buf);
- }
- puts("\n ");
+ puts("FPGA: ");
switch (unit_type) {
case UNITTYPE_CCD_SWITCH:
@@ -157,8 +172,6 @@ int checkboard(void)
printf(" %d channel(s)", feature_channels);
printf(", expansion %ssupported\n", feature_expansion ? "" : "un");
-
- return 0;
}
/*
@@ -169,6 +182,8 @@ int last_stage_init(void)
ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(0);
unsigned int k;
+ print_fpga_info();
+
miiphy_register(CONFIG_SYS_GBIT_MII_BUSNAME,
bb_miiphy_read, bb_miiphy_write);