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| author | Dirk Eibach <eibach@gdsys.de> | 2011-01-21 09:31:21 +0100 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2011-02-07 11:13:16 +0100 |
| commit | 2da0fc0d0fcdd991220cc120e5bc6d44991a5987 (patch) | |
| tree | c14838b5dbac4b29f646c72d0b460dd4c11dd83e /board/gdsys/405ep/io.c | |
| parent | 42d44f631c4e8e5359775bdc098f2fffde4e5c05 (diff) | |
| download | u-boot-imx-2da0fc0d0fcdd991220cc120e5bc6d44991a5987.zip u-boot-imx-2da0fc0d0fcdd991220cc120e5bc6d44991a5987.tar.gz u-boot-imx-2da0fc0d0fcdd991220cc120e5bc6d44991a5987.tar.bz2 | |
ppc4xx: Add DLVision-10G board support
Board support for the Guntermann & Drunck DLVision-10G.
Adds support for multiple FPGAs per board for gdsys 405ep
architecture.
Adds support for dual link osd hardware for gdsys 405ep.
Signed-off-by: Dirk Eibach <eibach@gdsys.de>
Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'board/gdsys/405ep/io.c')
| -rw-r--r-- | board/gdsys/405ep/io.c | 19 |
1 files changed, 7 insertions, 12 deletions
diff --git a/board/gdsys/405ep/io.c b/board/gdsys/405ep/io.c index 80877b6..0974019 100644 --- a/board/gdsys/405ep/io.c +++ b/board/gdsys/405ep/io.c @@ -29,7 +29,7 @@ #include <miiphy.h> -#include "../common/fpga.h" +#include <gdsys_fpga.h> #define PHYREG_CONTROL 0 #define PHYREG_PAGE_ADDRESS 22 @@ -37,13 +37,6 @@ #define PHYREG_PG2_COPPER_SPECIFIC_CONTROL_2 26 enum { - REG_VERSIONS = 0x0002, - REG_FPGA_FEATURES = 0x0004, - REG_FPGA_VERSION = 0x0006, - REG_QUAD_SERDES_RESET = 0x0012, -}; - -enum { UNITTYPE_CCD_SWITCH = 1, }; @@ -94,10 +87,11 @@ err_out: */ int checkboard(void) { + ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(0); char *s = getenv("serial#"); - u16 versions = fpga_get_reg(REG_VERSIONS); - u16 fpga_version = fpga_get_reg(REG_FPGA_VERSION); - u16 fpga_features = fpga_get_reg(REG_FPGA_FEATURES); + u16 versions = in_le16(&fpga->versions); + u16 fpga_version = in_le16(&fpga->fpga_version); + u16 fpga_features = in_le16(&fpga->fpga_features); unsigned unit_type; unsigned hardware_version; unsigned feature_channels; @@ -166,6 +160,7 @@ int checkboard(void) */ int last_stage_init(void) { + ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(0); unsigned int k; miiphy_register(CONFIG_SYS_GBIT_MII_BUSNAME, @@ -175,7 +170,7 @@ int last_stage_init(void) configure_gbit_phy(k); /* take fpga serdes blocks out of reset */ - fpga_set_reg(REG_QUAD_SERDES_RESET, 0); + out_le16(&fpga->quad_serdes_reset, 0); return 0; } |