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| author | Dirk Eibach <eibach@gdsys.de> | 2012-04-26 03:54:22 +0000 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2012-04-30 15:00:56 +0200 |
| commit | 6e9e6c36a6a52562edb3e3b93cbad33f9dfe5585 (patch) | |
| tree | d3088a2492fab0d3345bd284755d81b6355174ca /board/gdsys/405ep/dlvision-10g.c | |
| parent | 00251261e2d285323fc8440563d99c87ae4fc68d (diff) | |
| download | u-boot-imx-6e9e6c36a6a52562edb3e3b93cbad33f9dfe5585.zip u-boot-imx-6e9e6c36a6a52562edb3e3b93cbad33f9dfe5585.tar.gz u-boot-imx-6e9e6c36a6a52562edb3e3b93cbad33f9dfe5585.tar.bz2 | |
powerpc/ppc4xx: Make gdsys 405ep boards reset more generic
In order to add boards that have different hardware for fpga reset,
any 405ep gdsys board now provides these functions:
void gd405ep_init(void);
void gd405ep_set_fpga_reset(unsigned state);
void gd405ep_setup_hw(void);
int gd405ep_get_fpga_done(unsigned fpga);
Signed-off-by: Dirk Eibach <eibach@gdsys.de>
Cc: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'board/gdsys/405ep/dlvision-10g.c')
| -rw-r--r-- | board/gdsys/405ep/dlvision-10g.c | 36 |
1 files changed, 34 insertions, 2 deletions
diff --git a/board/gdsys/405ep/dlvision-10g.c b/board/gdsys/405ep/dlvision-10g.c index f55afbd..adaffb2 100644 --- a/board/gdsys/405ep/dlvision-10g.c +++ b/board/gdsys/405ep/dlvision-10g.c @@ -27,15 +27,18 @@ #include <asm/io.h> #include <asm/ppc4xx-gpio.h> +#include "405ep.h" #include <gdsys_fpga.h> #include "../common/osd.h" +#define LATCH0_BASE (CONFIG_SYS_LATCH_BASE) +#define LATCH1_BASE (CONFIG_SYS_LATCH_BASE + 0x100) #define LATCH2_BASE (CONFIG_SYS_LATCH_BASE + 0x200) -#define LATCH2_MC2_PRESENT_N 0x0080 - #define LATCH3_BASE (CONFIG_SYS_LATCH_BASE + 0x300) +#define LATCH2_MC2_PRESENT_N 0x0080 + enum { UNITTYPE_VIDEO_USER = 0, UNITTYPE_MAIN_USER = 1, @@ -261,3 +264,32 @@ int last_stage_init(void) return 0; } + +void gd405ep_init(void) +{ +} + +void gd405ep_set_fpga_reset(unsigned state) +{ + if (state) { + out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_RESET); + out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_RESET); + } else { + out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_BOOT); + out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_BOOT); + } +} + +void gd405ep_setup_hw(void) +{ + /* + * set "startup-finished"-gpios + */ + gpio_write_bit(21, 0); + gpio_write_bit(22, 1); +} + +int gd405ep_get_fpga_done(unsigned fpga) +{ + return in_le16((void *)LATCH2_BASE) & CONFIG_SYS_FPGA_DONE(fpga); +} |