Merge branch 'master' of git://git.denx.de/u-boot-ppc4xx

1 files changed, 53 insertions, 13 deletions

diff --git a/board/gdsys/405ep/405ep.c b/board/gdsys/405ep/405ep.c
index d3bd233..86a3ec8 100644
--- a/board/gdsys/405ep/405ep.c
+++ b/board/gdsys/405ep/405ep.c
@@ -26,8 +26,9 @@
 #include <asm/processor.h>
 #include <asm/io.h>
 #include <asm/ppc4xx-gpio.h>
+#include <asm/global_data.h>
 
-#include "../common/fpga.h"
+#include <gdsys_fpga.h>
 
 #define LATCH0_BASE (CONFIG_SYS_LATCH_BASE)
 #define LATCH1_BASE (CONFIG_SYS_LATCH_BASE + 0x100)
@@ -36,8 +37,29 @@
 #define REFLECTION_TESTPATTERN 0xdede
 #define REFLECTION_TESTPATTERN_INV (~REFLECTION_TESTPATTERN & 0xffff)
 
+DECLARE_GLOBAL_DATA_PTR;
+
+int get_fpga_state(unsigned dev)
+{
+	return gd->fpga_state[dev];
+}
+
+void print_fpga_state(unsigned dev)
+{
+	if (gd->fpga_state[dev] & FPGA_STATE_DONE_FAILED)
+		puts("       Waiting for FPGA-DONE timed out.\n");
+	if (gd->fpga_state[dev] & FPGA_STATE_REFLECTION_FAILED)
+		puts("       FPGA reflection test failed.\n");
+}
+
 int board_early_init_f(void)
 {
+	unsigned k;
+	unsigned ctr;
+
+	for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k)
+		gd->fpga_state[k] = 0;
+
 	mtdcr(UIC0SR, 0xFFFFFFFF);	/* clear all ints */
 	mtdcr(UIC0ER, 0x00000000);	/* disable all ints */
 	mtdcr(UIC0CR, 0x00000000);	/* set all to be non-critical */
@@ -66,10 +88,18 @@ int board_early_init_f(void)
 
 	/*
 	 * wait for fpga-done
-	 * fail ungraceful if fpga is not configuring properly
 	 */
-	while (!(in_le16((void *)LATCH2_BASE) & 0x0010))
-		;
+	for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) {
+		ctr = 0;
+		while (!(in_le16((void *)LATCH2_BASE)
+			& CONFIG_SYS_FPGA_DONE(k))) {
+			udelay(100000);
+			if (ctr++ > 5) {
+				gd->fpga_state[k] |= FPGA_STATE_DONE_FAILED;
+				break;
+			}
+		}
+	}
 
 	/*
 	 * setup io-latches for boot (stop reset)
@@ -78,15 +108,25 @@ int board_early_init_f(void)
 	out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_BOOT);
 	out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_BOOT);
 
-	/*
-	 * wait for fpga out of reset
-	 * fail ungraceful if fpga is not working properly
-	 */
-	while (1) {
-		fpga_set_reg(CONFIG_SYS_FPGA_RFL_LOW, REFLECTION_TESTPATTERN);
-		if (fpga_get_reg(CONFIG_SYS_FPGA_RFL_HIGH) ==
-			REFLECTION_TESTPATTERN_INV)
-			break;
+	for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) {
+		ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(k);
+		/*
+		 * wait for fpga out of reset
+		 */
+		ctr = 0;
+		while (1) {
+			out_le16(&fpga->reflection_low,
+				REFLECTION_TESTPATTERN);
+			if (in_le16(&fpga->reflection_high) ==
+				REFLECTION_TESTPATTERN_INV)
+				break;
+			udelay(100000);
+			if (ctr++ > 5) {
+				gd->fpga_state[k] |=
+					FPGA_STATE_REFLECTION_FAILED;
+				break;
+			}
+		}
 	}
 
 	return 0;