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authorDirk Eibach <eibach@gdsys.de>2011-01-21 09:31:21 +0100
committerStefan Roese <sr@denx.de>2011-02-07 11:13:16 +0100
commit2da0fc0d0fcdd991220cc120e5bc6d44991a5987 (patch)
treec14838b5dbac4b29f646c72d0b460dd4c11dd83e /board/gdsys/405ep/405ep.c
parent42d44f631c4e8e5359775bdc098f2fffde4e5c05 (diff)
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ppc4xx: Add DLVision-10G board support
Board support for the Guntermann & Drunck DLVision-10G. Adds support for multiple FPGAs per board for gdsys 405ep architecture. Adds support for dual link osd hardware for gdsys 405ep. Signed-off-by: Dirk Eibach <eibach@gdsys.de> Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'board/gdsys/405ep/405ep.c')
-rw-r--r--board/gdsys/405ep/405ep.c66
1 files changed, 53 insertions, 13 deletions
diff --git a/board/gdsys/405ep/405ep.c b/board/gdsys/405ep/405ep.c
index d3bd233..86a3ec8 100644
--- a/board/gdsys/405ep/405ep.c
+++ b/board/gdsys/405ep/405ep.c
@@ -26,8 +26,9 @@
#include <asm/processor.h>
#include <asm/io.h>
#include <asm/ppc4xx-gpio.h>
+#include <asm/global_data.h>
-#include "../common/fpga.h"
+#include <gdsys_fpga.h>
#define LATCH0_BASE (CONFIG_SYS_LATCH_BASE)
#define LATCH1_BASE (CONFIG_SYS_LATCH_BASE + 0x100)
@@ -36,8 +37,29 @@
#define REFLECTION_TESTPATTERN 0xdede
#define REFLECTION_TESTPATTERN_INV (~REFLECTION_TESTPATTERN & 0xffff)
+DECLARE_GLOBAL_DATA_PTR;
+
+int get_fpga_state(unsigned dev)
+{
+ return gd->fpga_state[dev];
+}
+
+void print_fpga_state(unsigned dev)
+{
+ if (gd->fpga_state[dev] & FPGA_STATE_DONE_FAILED)
+ puts(" Waiting for FPGA-DONE timed out.\n");
+ if (gd->fpga_state[dev] & FPGA_STATE_REFLECTION_FAILED)
+ puts(" FPGA reflection test failed.\n");
+}
+
int board_early_init_f(void)
{
+ unsigned k;
+ unsigned ctr;
+
+ for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k)
+ gd->fpga_state[k] = 0;
+
mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
mtdcr(UIC0ER, 0x00000000); /* disable all ints */
mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical */
@@ -66,10 +88,18 @@ int board_early_init_f(void)
/*
* wait for fpga-done
- * fail ungraceful if fpga is not configuring properly
*/
- while (!(in_le16((void *)LATCH2_BASE) & 0x0010))
- ;
+ for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) {
+ ctr = 0;
+ while (!(in_le16((void *)LATCH2_BASE)
+ & CONFIG_SYS_FPGA_DONE(k))) {
+ udelay(100000);
+ if (ctr++ > 5) {
+ gd->fpga_state[k] |= FPGA_STATE_DONE_FAILED;
+ break;
+ }
+ }
+ }
/*
* setup io-latches for boot (stop reset)
@@ -78,15 +108,25 @@ int board_early_init_f(void)
out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_BOOT);
out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_BOOT);
- /*
- * wait for fpga out of reset
- * fail ungraceful if fpga is not working properly
- */
- while (1) {
- fpga_set_reg(CONFIG_SYS_FPGA_RFL_LOW, REFLECTION_TESTPATTERN);
- if (fpga_get_reg(CONFIG_SYS_FPGA_RFL_HIGH) ==
- REFLECTION_TESTPATTERN_INV)
- break;
+ for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) {
+ ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(k);
+ /*
+ * wait for fpga out of reset
+ */
+ ctr = 0;
+ while (1) {
+ out_le16(&fpga->reflection_low,
+ REFLECTION_TESTPATTERN);
+ if (in_le16(&fpga->reflection_high) ==
+ REFLECTION_TESTPATTERN_INV)
+ break;
+ udelay(100000);
+ if (ctr++ > 5) {
+ gd->fpga_state[k] |=
+ FPGA_STATE_REFLECTION_FAILED;
+ break;
+ }
+ }
}
return 0;