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authorStefan Roese <sr@denx.de>2009-09-24 13:59:57 +0200
committerStefan Roese <sr@denx.de>2009-09-28 10:45:54 +0200
commit95b602bab5fec2fffab07a01ea3947c70d1bacc1 (patch)
treeacee523787d213090cc592029f1d566473bc1fd7 /board/g2000
parent952e7760bfc5b0e3b142b9ce34e7fbb7d008c900 (diff)
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ppc4xx: Convert PPC4xx SDRAM defines from lower case to upper case
The latest PPC4xx register cleanup patch missed some SDRAM defines. This patch now changes lower case UIC defines to upper case. Also some names are changed to match the naming in the IBM/AMCC users manuals (e.g. mem_mcopt1 -> SDRAM0_CFG). Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'board/g2000')
-rw-r--r--board/g2000/g2000.c14
1 files changed, 7 insertions, 7 deletions
diff --git a/board/g2000/g2000.c b/board/g2000/g2000.c
index 8afffdc..092a3d8 100644
--- a/board/g2000/g2000.c
+++ b/board/g2000/g2000.c
@@ -116,16 +116,16 @@ long int init_sdram_static_settings(void)
{
#define mtsdram0(reg, data) mtdcr(SDRAM0_CFGADDR,reg);mtdcr(SDRAM0_CFGDATA,data)
/* disable memcontroller so updates work */
- mtsdram0( mem_mcopt1, MEM_MCOPT1_INIT_VAL );
- mtsdram0( mem_rtr , MEM_RTR_INIT_VAL );
- mtsdram0( mem_pmit , MEM_PMIT_INIT_VAL );
- mtsdram0( mem_mb0cf , MEM_MB0CF_INIT_VAL );
- mtsdram0( mem_mb1cf , MEM_MB1CF_INIT_VAL );
- mtsdram0( mem_sdtr1 , MEM_SDTR1_INIT_VAL );
+ mtsdram0( SDRAM0_CFG, MEM_MCOPT1_INIT_VAL );
+ mtsdram0( SDRAM0_RTR , MEM_RTR_INIT_VAL );
+ mtsdram0( SDRAM0_PMIT , MEM_PMIT_INIT_VAL );
+ mtsdram0( SDRAM0_B0CR , MEM_MB0CF_INIT_VAL );
+ mtsdram0( SDRAM0_B1CR , MEM_MB1CF_INIT_VAL );
+ mtsdram0( SDRAM0_TR , MEM_SDTR1_INIT_VAL );
/* SDRAM have a power on delay, 500 micro should do */
udelay(500);
- mtsdram0( mem_mcopt1, MEM_MCOPT1_INIT_VAL|SDRAM0_CFG_ENABLE );
+ mtsdram0( SDRAM0_CFG, MEM_MCOPT1_INIT_VAL|SDRAM0_CFG_ENABLE );
return (CONFIG_SYS_SDRAM_SIZE); /* CONFIG_SYS_SDRAM_SIZE is in G2000.h */
}