Merge git://git.denx.de/u-boot into u-boot

36 files changed, 282 insertions, 125 deletions

diff --git a/board/freescale/mpc8315erdb/mpc8315erdb.c b/board/freescale/mpc8315erdb/mpc8315erdb.c
index ea4b04f..f80b0ba 100644
--- a/board/freescale/mpc8315erdb/mpc8315erdb.c
+++ b/board/freescale/mpc8315erdb/mpc8315erdb.c
@@ -30,6 +30,7 @@
 #include <pci.h>
 #include <mpc83xx.h>
 #include <netdev.h>
+#include <asm/io.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -95,12 +96,45 @@ static struct pci_region pci_regions[] = {
 	}
 };
 
+static struct pci_region pcie_regions_0[] = {
+	{
+		.bus_start = CONFIG_SYS_PCIE1_MEM_BASE,
+		.phys_start = CONFIG_SYS_PCIE1_MEM_PHYS,
+		.size = CONFIG_SYS_PCIE1_MEM_SIZE,
+		.flags = PCI_REGION_MEM,
+	},
+	{
+		.bus_start = CONFIG_SYS_PCIE1_IO_BASE,
+		.phys_start = CONFIG_SYS_PCIE1_IO_PHYS,
+		.size = CONFIG_SYS_PCIE1_IO_SIZE,
+		.flags = PCI_REGION_IO,
+	},
+};
+
+static struct pci_region pcie_regions_1[] = {
+	{
+		.bus_start = CONFIG_SYS_PCIE2_MEM_BASE,
+		.phys_start = CONFIG_SYS_PCIE2_MEM_PHYS,
+		.size = CONFIG_SYS_PCIE2_MEM_SIZE,
+		.flags = PCI_REGION_MEM,
+	},
+	{
+		.bus_start = CONFIG_SYS_PCIE2_IO_BASE,
+		.phys_start = CONFIG_SYS_PCIE2_IO_PHYS,
+		.size = CONFIG_SYS_PCIE2_IO_SIZE,
+		.flags = PCI_REGION_IO,
+	},
+};
+
 void pci_init_board(void)
 {
 	volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
+	volatile sysconf83xx_t *sysconf = &immr->sysconf;
 	volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
 	volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
+	volatile law83xx_t *pcie_law = sysconf->pcielaw;
 	struct pci_region *reg[] = { pci_regions };
+	struct pci_region *pcie_reg[] = { pcie_regions_0, pcie_regions_1, };
 	int warmboot;
 
 	/* Enable all 3 PCI_CLK_OUTPUTs. */
@@ -119,6 +153,24 @@ void pci_init_board(void)
 	warmboot |= immr->pmc.pmccr1 & PMCCR1_POWER_OFF;
 
 	mpc83xx_pci_init(1, reg, warmboot);
+
+	/* Configure the clock for PCIE controller */
+	clrsetbits_be32(&clk->sccr, SCCR_PCIEXP1CM | SCCR_PCIEXP2CM,
+				    SCCR_PCIEXP1CM_1 | SCCR_PCIEXP2CM_1);
+
+	/* Deassert the resets in the control register */
+	out_be32(&sysconf->pecr1, 0xE0008000);
+	out_be32(&sysconf->pecr2, 0xE0008000);
+	udelay(2000);
+
+	/* Configure PCI Express Local Access Windows */
+	out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR);
+	out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB);
+
+	out_be32(&pcie_law[1].bar, CONFIG_SYS_PCIE2_BASE & LAWBAR_BAR);
+	out_be32(&pcie_law[1].ar, LBLAWAR_EN | LBLAWAR_512MB);
+
+	mpc83xx_pcie_init(2, pcie_reg, warmboot);
 }
 
 #if defined(CONFIG_OF_BOARD_SETUP)
diff --git a/board/freescale/mpc8349emds/pci.c b/board/freescale/mpc8349emds/pci.c
index ad7bf5d..af0b1da 100644
--- a/board/freescale/mpc8349emds/pci.c
+++ b/board/freescale/mpc8349emds/pci.c
@@ -171,15 +171,10 @@ void pci_init_board(void)
 void pci_init_board(void)
 {
 	volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
-	volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
 	volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
 	volatile pcictrl83xx_t *pci_ctrl = &immr->pci_ctrl[0];
 	struct pci_region *reg[] = { pci1_regions };
 
-	/* Enable all 8 PCI_CLK_OUTPUTS */
-	clk->occr = 0xff000000;
-	udelay(2000);
-
 	/* Configure PCI Local Access Windows */
 	pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
 	pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G;
@@ -187,8 +182,6 @@ void pci_init_board(void)
 	pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
 	pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_4M;
 
-	udelay(2000);
-
 	mpc83xx_pci_init(1, reg, 0);
 
 	/* Configure PCI Inbound Translation Windows (3 1MB windows) */
diff --git a/board/freescale/mpc837xemds/mpc837xemds.c b/board/freescale/mpc837xemds/mpc837xemds.c
index acf8ada..156d808 100644
--- a/board/freescale/mpc837xemds/mpc837xemds.c
+++ b/board/freescale/mpc837xemds/mpc837xemds.c
@@ -18,6 +18,7 @@
 #include <tsec.h>
 #include <libfdt.h>
 #include <fdt_support.h>
+#include "pci.h"
 #include "../common/pq-mds-pib.h"
 
 int board_early_init_f(void)
@@ -38,14 +39,10 @@ int board_early_init_f(void)
 	case SPR_8377:
 		fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA,
 				 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
-		fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX,
-				 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
 		break;
 	case SPR_8378:
 		fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SGMII,
 				 FSL_SERDES_CLK_125, FSL_SERDES_VDD_1V);
-		fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX,
-				 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
 		break;
 	case SPR_8379:
 		fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA,
@@ -316,6 +313,7 @@ void ft_board_setup(void *blob, bd_t *bd)
 	ft_pci_setup(blob, bd);
 	if (board_pci_host_broken())
 		ft_pci_fixup(blob, bd);
+	ft_pcie_fixup(blob, bd);
 #endif
 }
 #endif /* CONFIG_OF_BOARD_SETUP */
diff --git a/board/freescale/mpc837xemds/pci.c b/board/freescale/mpc837xemds/pci.c
index df4e748..31116b3 100644
--- a/board/freescale/mpc837xemds/pci.c
+++ b/board/freescale/mpc837xemds/pci.c
@@ -16,7 +16,9 @@
 #include <mpc83xx.h>
 #include <pci.h>
 #include <i2c.h>
+#include <fdt_support.h>
 #include <asm/fsl_i2c.h>
+#include <asm/fsl_serdes.h>
 
 #if defined(CONFIG_PCI)
 static struct pci_region pci_regions[] = {
@@ -40,15 +42,59 @@ static struct pci_region pci_regions[] = {
 	}
 };
 
+static struct pci_region pcie_regions_0[] = {
+	{
+		.bus_start = CONFIG_SYS_PCIE1_MEM_BASE,
+		.phys_start = CONFIG_SYS_PCIE1_MEM_PHYS,
+		.size = CONFIG_SYS_PCIE1_MEM_SIZE,
+		.flags = PCI_REGION_MEM,
+	},
+	{
+		.bus_start = CONFIG_SYS_PCIE1_IO_BASE,
+		.phys_start = CONFIG_SYS_PCIE1_IO_PHYS,
+		.size = CONFIG_SYS_PCIE1_IO_SIZE,
+		.flags = PCI_REGION_IO,
+	},
+};
+
+static struct pci_region pcie_regions_1[] = {
+	{
+		.bus_start = CONFIG_SYS_PCIE2_MEM_BASE,
+		.phys_start = CONFIG_SYS_PCIE2_MEM_PHYS,
+		.size = CONFIG_SYS_PCIE2_MEM_SIZE,
+		.flags = PCI_REGION_MEM,
+	},
+	{
+		.bus_start = CONFIG_SYS_PCIE2_IO_BASE,
+		.phys_start = CONFIG_SYS_PCIE2_IO_PHYS,
+		.size = CONFIG_SYS_PCIE2_IO_SIZE,
+		.flags = PCI_REGION_IO,
+	},
+};
+
+static int is_pex_x2(void)
+{
+	const char *pex_x2 = getenv("pex_x2");
+
+	if (pex_x2 && !strcmp(pex_x2, "yes"))
+		return 1;
+	return 0;
+}
+
 void pci_init_board(void)
 {
 	volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
+	volatile sysconf83xx_t *sysconf = &immr->sysconf;
 	volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
 	volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
+	volatile law83xx_t *pcie_law = sysconf->pcielaw;
 	struct pci_region *reg[] = { pci_regions };
+	struct pci_region *pcie_reg[] = { pcie_regions_0, pcie_regions_1, };
+	u32 spridr = in_be32(&immr->sysconf.spridr);
+	int pex2 = is_pex_x2();
 
 	if (board_pci_host_broken())
-		return;
+		goto skip_pci;
 
 	/* Enable all 5 PCI_CLK_OUTPUTS */
 	clk->occr |= 0xf8000000;
@@ -64,5 +110,46 @@ void pci_init_board(void)
 	udelay(2000);
 
 	mpc83xx_pci_init(1, reg, 0);
+skip_pci:
+	/* There is no PEX in MPC8379 parts. */
+	if (PARTID_NO_E(spridr) == SPR_8379)
+		return;
+
+	/* Configure the clock for PCIE controller */
+	clrsetbits_be32(&clk->sccr, SCCR_PCIEXP1CM | SCCR_PCIEXP2CM,
+				    SCCR_PCIEXP1CM_1 | SCCR_PCIEXP2CM_1);
+
+	/* Deassert the resets in the control register */
+	out_be32(&sysconf->pecr1, 0xE0008000);
+	if (!pex2)
+		out_be32(&sysconf->pecr2, 0xE0008000);
+	udelay(2000);
+
+	/* Configure PCI Express Local Access Windows */
+	out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR);
+	out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB);
+
+	out_be32(&pcie_law[1].bar, CONFIG_SYS_PCIE2_BASE & LAWBAR_BAR);
+	out_be32(&pcie_law[1].ar, LBLAWAR_EN | LBLAWAR_512MB);
+
+	if (pex2)
+		fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX_X2,
+				 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
+	else
+		fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX,
+				 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
+
+	mpc83xx_pcie_init(pex2 ? 1 : 2, pcie_reg, 0);
+}
+
+void ft_pcie_fixup(void *blob, bd_t *bd)
+{
+	const char *status = "disabled (PCIE1 is x2)";
+
+	if (!is_pex_x2())
+		return;
+
+	do_fixup_by_path(blob, "pci2", "status", status,
+			 strlen(status) + 1, 1);
 }
 #endif /* CONFIG_PCI */
diff --git a/board/freescale/mpc837xemds/pci.h b/board/freescale/mpc837xemds/pci.h
new file mode 100644
index 0000000..fd7a916
--- /dev/null
+++ b/board/freescale/mpc837xemds/pci.h
@@ -0,0 +1,6 @@
+#ifndef __BOARD_MPC837XEMDS_PCI_H
+#define __BOARD_MPC837XEMDS_PCI_H
+
+extern void ft_pcie_fixup(void *blob, bd_t *bd);
+
+#endif /* __BOARD_MPC837XEMDS_PCI_H */
diff --git a/board/freescale/mpc8536ds/ddr.c b/board/freescale/mpc8536ds/ddr.c
index 3135d6d..2bad787 100644
--- a/board/freescale/mpc8536ds/ddr.c
+++ b/board/freescale/mpc8536ds/ddr.c
@@ -79,4 +79,10 @@ void fsl_ddr_board_options(memctl_options_t *popts,
 	 *	- number of DIMMs installed
 	 */
 	popts->half_strength_driver_enable = 0;
+
+	/*
+	 * For wake up arp feature, we need enable auto self refresh
+	 */
+	popts->auto_self_refresh_en = 1;
+	popts->sr_it = 0x6;
 }
diff --git a/board/freescale/mpc8536ds/law.c b/board/freescale/mpc8536ds/law.c
index 0861fa7..31614d2 100644
--- a/board/freescale/mpc8536ds/law.c
+++ b/board/freescale/mpc8536ds/law.c
@@ -30,14 +30,14 @@
 struct law_entry law_table[] = {
 	SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCI),
 	SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCI),
-	SET_LAW(CONFIG_SYS_FLASH_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
+	SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
 	SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAWAR_SIZE_128M, LAW_TRGT_IF_PCIE_1),
 	SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_1),
 	SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAWAR_SIZE_128M, LAW_TRGT_IF_PCIE_2),
 	SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_2),
 	SET_LAW(CONFIG_SYS_PCIE3_MEM_PHYS, LAWAR_SIZE_512M, LAW_TRGT_IF_PCIE_3),
 	SET_LAW(CONFIG_SYS_PCIE3_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_3),
-	SET_LAW(PIXIS_BASE, LAW_SIZE_4K, LAW_TRGT_IF_LBC),
+	SET_LAW(PIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_LBC),
 	SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
 };
 
diff --git a/board/freescale/mpc8536ds/mpc8536ds.c b/board/freescale/mpc8536ds/mpc8536ds.c
index 2b17612..1e2e2dc 100644
--- a/board/freescale/mpc8536ds/mpc8536ds.c
+++ b/board/freescale/mpc8536ds/mpc8536ds.c
@@ -192,14 +192,14 @@ pci_init_board(void)
 
 		/* outbound memory */
 		pci_set_region(r++,
-			       CONFIG_SYS_PCIE3_MEM_BASE,
+			       CONFIG_SYS_PCIE3_MEM_BUS,
 			       CONFIG_SYS_PCIE3_MEM_PHYS,
 			       CONFIG_SYS_PCIE3_MEM_SIZE,
 			       PCI_REGION_MEM);
 
 		/* outbound io */
 		pci_set_region(r++,
-			       CONFIG_SYS_PCIE3_IO_BASE,
+			       CONFIG_SYS_PCIE3_IO_BUS,
 			       CONFIG_SYS_PCIE3_IO_PHYS,
 			       CONFIG_SYS_PCIE3_IO_SIZE,
 			       PCI_REGION_IO);
@@ -247,22 +247,22 @@ pci_init_board(void)
 
 		/* outbound memory */
 		pci_set_region(r++,
-			       CONFIG_SYS_PCIE1_MEM_BASE,
+			       CONFIG_SYS_PCIE1_MEM_BUS,
 			       CONFIG_SYS_PCIE1_MEM_PHYS,
 			       CONFIG_SYS_PCIE1_MEM_SIZE,
 			       PCI_REGION_MEM);
 
 		/* outbound io */
 		pci_set_region(r++,
-			       CONFIG_SYS_PCIE1_IO_BASE,
+			       CONFIG_SYS_PCIE1_IO_BUS,
 			       CONFIG_SYS_PCIE1_IO_PHYS,
 			       CONFIG_SYS_PCIE1_IO_SIZE,
 			       PCI_REGION_IO);
 
-#ifdef CONFIG_SYS_PCIE1_MEM_BASE2
+#ifdef CONFIG_SYS_PCIE1_MEM_BUS2
 		/* outbound memory */
 		pci_set_region(r++,
-			       CONFIG_SYS_PCIE1_MEM_BASE2,
+			       CONFIG_SYS_PCIE1_MEM_BUS2,
 			       CONFIG_SYS_PCIE1_MEM_PHYS2,
 			       CONFIG_SYS_PCIE1_MEM_SIZE2,
 			       PCI_REGION_MEM);
@@ -310,22 +310,22 @@ pci_init_board(void)
 
 		/* outbound memory */
 		pci_set_region(r++,
-			       CONFIG_SYS_PCIE2_MEM_BASE,
+			       CONFIG_SYS_PCIE2_MEM_BUS,
 			       CONFIG_SYS_PCIE2_MEM_PHYS,
 			       CONFIG_SYS_PCIE2_MEM_SIZE,
 			       PCI_REGION_MEM);
 
 		/* outbound io */
 		pci_set_region(r++,
-			       CONFIG_SYS_PCIE2_IO_BASE,
+			       CONFIG_SYS_PCIE2_IO_BUS,
 			       CONFIG_SYS_PCIE2_IO_PHYS,
 			       CONFIG_SYS_PCIE2_IO_SIZE,
 			       PCI_REGION_IO);
 
-#ifdef CONFIG_SYS_PCIE2_MEM_BASE2
+#ifdef CONFIG_SYS_PCIE2_MEM_BUS2
 		/* outbound memory */
 		pci_set_region(r++,
-			       CONFIG_SYS_PCIE2_MEM_BASE2,
+			       CONFIG_SYS_PCIE2_MEM_BUS2,
 			       CONFIG_SYS_PCIE2_MEM_PHYS2,
 			       CONFIG_SYS_PCIE2_MEM_SIZE2,
 			       PCI_REGION_MEM);
@@ -378,22 +378,22 @@ pci_init_board(void)
 
 		/* outbound memory */
 		pci_set_region(r++,
-			       CONFIG_SYS_PCI1_MEM_BASE,
+			       CONFIG_SYS_PCI1_MEM_BUS,
 			       CONFIG_SYS_PCI1_MEM_PHYS,
 			       CONFIG_SYS_PCI1_MEM_SIZE,
 			       PCI_REGION_MEM);
 
 		/* outbound io */
 		pci_set_region(r++,
-			       CONFIG_SYS_PCI1_IO_BASE,
+			       CONFIG_SYS_PCI1_IO_BUS,
 			       CONFIG_SYS_PCI1_IO_PHYS,
 			       CONFIG_SYS_PCI1_IO_SIZE,
 			       PCI_REGION_IO);
 
-#ifdef CONFIG_SYS_PCI1_MEM_BASE2
+#ifdef CONFIG_SYS_PCI1_MEM_BUS2
 		/* outbound memory */
 		pci_set_region(r++,
-			       CONFIG_SYS_PCI1_MEM_BASE2,
+			       CONFIG_SYS_PCI1_MEM_BUS2,
 			       CONFIG_SYS_PCI1_MEM_PHYS2,
 			       CONFIG_SYS_PCI1_MEM_SIZE2,
 			       PCI_REGION_MEM);
@@ -433,7 +433,7 @@ int board_early_init_r(void)
 	/* invalidate existing TLB entry for flash + promjet */
 	disable_tlb(flash_esel);
 
-	set_tlb(1, flashbase, flashbase,		/* tlb, epn, rpn */
+	set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,	/* tlb, epn, rpn */
 		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,	/* perms, wimge */
 		0, flash_esel, BOOKE_PAGESZ_256M, 1);	/* ts, esel, tsize, iprot */
 
diff --git a/board/freescale/mpc8536ds/tlb.c b/board/freescale/mpc8536ds/tlb.c
index c81a959..35a13d4 100644
--- a/board/freescale/mpc8536ds/tlb.c
+++ b/board/freescale/mpc8536ds/tlb.c
@@ -41,7 +41,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 0, BOOKE_PAGESZ_4K, 0),
 
-	SET_TLB_ENTRY(0, PIXIS_BASE, PIXIS_BASE,
+	SET_TLB_ENTRY(0, PIXIS_BASE, PIXIS_BASE_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 0, BOOKE_PAGESZ_4K, 0),
 
@@ -53,17 +53,17 @@ struct fsl_e_tlb_entry tlb_table[] = {
 
 	/* W**G* - Flash/promjet, localbus */
 	/* This will be changed to *I*G* after relocation to RAM. */
-	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE,
+	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
 		      MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
 		      0, 1, BOOKE_PAGESZ_256M, 1),
 
 	/* *I*G* - PCI */
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS,
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT, CONFIG_SYS_PCI1_MEM_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 2, BOOKE_PAGESZ_1G, 1),
 
 	/* *I*G* - PCI I/O */
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_IO_PHYS, CONFIG_SYS_PCI1_IO_PHYS,
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_IO_VIRT, CONFIG_SYS_PCI1_IO_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 3, BOOKE_PAGESZ_256K, 1),
 
diff --git a/board/freescale/mpc8540ads/ddr.c b/board/freescale/mpc8540ads/ddr.c
index 7850794..93d1100 100644
--- a/board/freescale/mpc8540ads/ddr.c
+++ b/board/freescale/mpc8540ads/ddr.c
@@ -65,6 +65,9 @@ void fsl_ddr_board_options(memctl_options_t *popts,
 	 */
 	popts->write_data_delay = 3;
 
+	/* 2T timing enable */
+	popts->twoT_en = 1;
+
 	/*
 	 * Factors to consider for half-strength driver enable:
 	 *	- number of DIMMs installed
diff --git a/board/freescale/mpc8540ads/law.c b/board/freescale/mpc8540ads/law.c
index 7dd8f29..f5644e1 100644
--- a/board/freescale/mpc8540ads/law.c
+++ b/board/freescale/mpc8540ads/law.c
@@ -52,7 +52,7 @@ struct law_entry law_table[] = {
 	/* This is not so much the SDRAM map as it is the whole localbus map. */
 	SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
 	SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI),
-	SET_LAW(CONFIG_SYS_RIO_MEM_BASE, LAWAR_SIZE_512M, LAW_TRGT_IF_RIO),
+	SET_LAW(CONFIG_SYS_RIO_MEM_PHYS, LAWAR_SIZE_512M, LAW_TRGT_IF_RIO),
 };
 
 int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/mpc8540ads/mpc8540ads.c b/board/freescale/mpc8540ads/mpc8540ads.c
index a0b6fbd..9e3f677 100644
--- a/board/freescale/mpc8540ads/mpc8540ads.c
+++ b/board/freescale/mpc8540ads/mpc8540ads.c
@@ -133,7 +133,7 @@ local_bus_init(void)
 	 */
 
 	get_sys_info(&sysinfo);
-	clkdiv = lbc->lcrr & 0x0f;
+	clkdiv = lbc->lcrr & LCRR_CLKDIV;
 	lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
 
 	if (lbc_hz < 66) {
diff --git a/board/freescale/mpc8540ads/tlb.c b/board/freescale/mpc8540ads/tlb.c
index 2ec3ccc..a9925d5 100644
--- a/board/freescale/mpc8540ads/tlb.c
+++ b/board/freescale/mpc8540ads/tlb.c
@@ -54,7 +54,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
 	 * TLB 1:	256M	Non-cacheable, guarded
 	 * 0x80000000	256M	PCI1 MEM First half
 	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS,
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT, CONFIG_SYS_PCI1_MEM_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 1, BOOKE_PAGESZ_256M, 1),
 
@@ -62,7 +62,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
 	 * TLB 2:	256M	Non-cacheable, guarded
 	 * 0x90000000	256M	PCI1 MEM Second half
 	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000,
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT + 0x10000000, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 2, BOOKE_PAGESZ_256M, 1),
 
@@ -70,7 +70,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
 	 * TLB 3:	256M	Non-cacheable, guarded
 	 * 0xc0000000	256M	Rapid IO MEM First half
 	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BASE, CONFIG_SYS_RIO_MEM_BASE,
+	SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_VIRT, CONFIG_SYS_RIO_MEM_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 3, BOOKE_PAGESZ_256M, 1),
 
@@ -78,7 +78,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
 	 * TLB 4:	256M	Non-cacheable, guarded
 	 * 0xd0000000	256M	Rapid IO MEM Second half
 	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BASE + 0x10000000, CONFIG_SYS_RIO_MEM_BASE + 0x10000000,
+	SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_VIRT + 0x10000000, CONFIG_SYS_RIO_MEM_PHYS + 0x10000000,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 4, BOOKE_PAGESZ_256M, 1),
 
diff --git a/board/freescale/mpc8541cds/mpc8541cds.c b/board/freescale/mpc8541cds/mpc8541cds.c
index 7e40c5c..e6025c8 100644
--- a/board/freescale/mpc8541cds/mpc8541cds.c
+++ b/board/freescale/mpc8541cds/mpc8541cds.c
@@ -308,7 +308,7 @@ local_bus_init(void)
 	 */
 
 	get_sys_info(&sysinfo);
-	clkdiv = lbc->lcrr & 0x0f;
+	clkdiv = lbc->lcrr & LCRR_CLKDIV;
 	lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
 
 	if (lbc_hz < 66) {
diff --git a/board/freescale/mpc8541cds/tlb.c b/board/freescale/mpc8541cds/tlb.c
index bf957c0..ae6812f 100644
--- a/board/freescale/mpc8541cds/tlb.c
+++ b/board/freescale/mpc8541cds/tlb.c
@@ -54,7 +54,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
 	 * TLB 1:	256M	Non-cacheable, guarded
 	 * 0x80000000	256M	PCI1 MEM First half
 	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS,
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT, CONFIG_SYS_PCI1_MEM_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 1, BOOKE_PAGESZ_256M, 1),
 
@@ -62,7 +62,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
 	 * TLB 2:	256M	Non-cacheable, guarded
 	 * 0x90000000	256M	PCI1 MEM Second half
 	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000,
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT + 0x10000000, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 2, BOOKE_PAGESZ_256M, 1),
 
@@ -70,7 +70,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
 	 * TLB 3:	256M	Non-cacheable, guarded
 	 * 0xa0000000	256M	PCI2 MEM First half
 	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCI2_MEM_PHYS, CONFIG_SYS_PCI2_MEM_PHYS,
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCI2_MEM_VIRT, CONFIG_SYS_PCI2_MEM_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 3, BOOKE_PAGESZ_256M, 1),
 
@@ -78,7 +78,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
 	 * TLB 4:	256M	Non-cacheable, guarded
 	 * 0xb0000000	256M	PCI2 MEM Second half
 	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCI2_MEM_PHYS + 0x10000000, CONFIG_SYS_PCI2_MEM_PHYS + 0x10000000,
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCI2_MEM_VIRT + 0x10000000, CONFIG_SYS_PCI2_MEM_PHYS + 0x10000000,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 4, BOOKE_PAGESZ_256M, 1),
 
diff --git a/board/freescale/mpc8544ds/ddr.c b/board/freescale/mpc8544ds/ddr.c
index 34f84a2..b8330eb 100644
--- a/board/freescale/mpc8544ds/ddr.c
+++ b/board/freescale/mpc8544ds/ddr.c
@@ -75,6 +75,9 @@ void fsl_ddr_board_options(memctl_options_t *popts,
 	 */
 	popts->write_data_delay = 3;
 
+	/* 2T timing enable */
+	popts->twoT_en = 1;
+
 	/*
 	 * Factors to consider for half-strength driver enable:
 	 *	- number of DIMMs installed
diff --git a/board/freescale/mpc8544ds/mpc8544ds.c b/board/freescale/mpc8544ds/mpc8544ds.c
index 14581ab..7ff5a9b 100644
--- a/board/freescale/mpc8544ds/mpc8544ds.c
+++ b/board/freescale/mpc8544ds/mpc8544ds.c
@@ -121,7 +121,7 @@ pci_init_board(void)
 	volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE3_ADDR;
 	struct pci_controller *hose = &pcie3_hose;
 	int pcie_ep = (host_agent == 1);
-	int pcie_configured  = io_sel >= 1;
+	int pcie_configured  = io_sel >= 6;
 	struct pci_region *r = hose->regions;
 
 	if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
@@ -139,22 +139,22 @@ pci_init_board(void)
 
 		/* outbound memory */
 		pci_set_region(r++,
-			       CONFIG_SYS_PCIE3_MEM_BASE,
+			       CONFIG_SYS_PCIE3_MEM_BUS,
 			       CONFIG_SYS_PCIE3_MEM_PHYS,
 			       CONFIG_SYS_PCIE3_MEM_SIZE,
 			       PCI_REGION_MEM);
 
 		/* outbound io */
 		pci_set_region(r++,
-			       CONFIG_SYS_PCIE3_IO_BASE,
+			       CONFIG_SYS_PCIE3_IO_BUS,
 			       CONFIG_SYS_PCIE3_IO_PHYS,
 			       CONFIG_SYS_PCIE3_IO_SIZE,
 			       PCI_REGION_IO);
 
-#ifdef CONFIG_SYS_PCIE3_MEM_BASE2
+#ifdef CONFIG_SYS_PCIE3_MEM_BUS2
 		/* outbound memory */
 		pci_set_region(r++,
-			       CONFIG_SYS_PCIE3_MEM_BASE2,
+			       CONFIG_SYS_PCIE3_MEM_BUS2,
 			       CONFIG_SYS_PCIE3_MEM_PHYS2,
 			       CONFIG_SYS_PCIE3_MEM_SIZE2,
 			       PCI_REGION_MEM);
@@ -173,7 +173,7 @@ pci_init_board(void)
 		 * Activate ULI1575 legacy chip by performing a fake
 		 * memory access.  Needed to make ULI RTC work.
 		 */
-		in_be32((u32 *)CONFIG_SYS_PCIE3_MEM_BASE);
+		in_be32((u32 *)CONFIG_SYS_PCIE3_MEM_BUS);
 	} else {
 		printf ("    PCIE3: disabled\n");
 	}
@@ -188,7 +188,7 @@ pci_init_board(void)
 	volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
 	struct pci_controller *hose = &pcie1_hose;
 	int pcie_ep = (host_agent == 5);
-	int pcie_configured  = io_sel & 6;
+	int pcie_configured  = io_sel >= 2;
 	struct pci_region *r = hose->regions;
 
 	if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
@@ -206,22 +206,22 @@ pci_init_board(void)
 
 		/* outbound memory */
 		pci_set_region(r++,
-			       CONFIG_SYS_PCIE1_MEM_BASE,
+			       CONFIG_SYS_PCIE1_MEM_BUS,
 			       CONFIG_SYS_PCIE1_MEM_PHYS,
 			       CONFIG_SYS_PCIE1_MEM_SIZE,
 			       PCI_REGION_MEM);
 
 		/* outbound io */
 		pci_set_region(r++,
-			       CONFIG_SYS_PCIE1_IO_BASE,
+			       CONFIG_SYS_PCIE1_IO_BUS,
 			       CONFIG_SYS_PCIE1_IO_PHYS,
 			       CONFIG_SYS_PCIE1_IO_SIZE,
 			       PCI_REGION_IO);
 
-#ifdef CONFIG_SYS_PCIE1_MEM_BASE2
+#ifdef CONFIG_SYS_PCIE1_MEM_BUS2
 		/* outbound memory */
 		pci_set_region(r++,
-			       CONFIG_SYS_PCIE1_MEM_BASE2,
+			       CONFIG_SYS_PCIE1_MEM_BUS2,
 			       CONFIG_SYS_PCIE1_MEM_PHYS2,
 			       CONFIG_SYS_PCIE1_MEM_SIZE2,
 			       PCI_REGION_MEM);
@@ -251,7 +251,7 @@ pci_init_board(void)
 	volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR;
 	struct pci_controller *hose = &pcie2_hose;
 	int pcie_ep = (host_agent == 3);
-	int pcie_configured  = io_sel & 4;
+	int pcie_configured  = io_sel >= 4;
 	struct pci_region *r = hose->regions;
 
 	if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
@@ -269,22 +269,22 @@ pci_init_board(void)
 
 		/* outbound memory */
 		pci_set_region(r++,
-			       CONFIG_SYS_PCIE2_MEM_BASE,
+			       CONFIG_SYS_PCIE2_MEM_BUS,
 			       CONFIG_SYS_PCIE2_MEM_PHYS,
 			       CONFIG_SYS_PCIE2_MEM_SIZE,
 			       PCI_REGION_MEM);
 
 		/* outbound io */
 		pci_set_region(r++,
-			       CONFIG_SYS_PCIE2_IO_BASE,
+			       CONFIG_SYS_PCIE2_IO_BUS,
 			       CONFIG_SYS_PCIE2_IO_PHYS,
 			       CONFIG_SYS_PCIE2_IO_SIZE,
 			       PCI_REGION_IO);
 
-#ifdef CONFIG_SYS_PCIE2_MEM_BASE2
+#ifdef CONFIG_SYS_PCIE2_MEM_BUS2
 		/* outbound memory */
 		pci_set_region(r++,
-			       CONFIG_SYS_PCIE2_MEM_BASE2,
+			       CONFIG_SYS_PCIE2_MEM_BUS2,
 			       CONFIG_SYS_PCIE2_MEM_PHYS2,
 			       CONFIG_SYS_PCIE2_MEM_SIZE2,
 			       PCI_REGION_MEM);
@@ -337,22 +337,22 @@ pci_init_board(void)
 
 		/* outbound memory */
 		pci_set_region(r++,
-			       CONFIG_SYS_PCI1_MEM_BASE,
+			       CONFIG_SYS_PCI1_MEM_BUS,
 			       CONFIG_SYS_PCI1_MEM_PHYS,
 			       CONFIG_SYS_PCI1_MEM_SIZE,
 			       PCI_REGION_MEM);
 
 		/* outbound io */
 		pci_set_region(r++,
-			       CONFIG_SYS_PCI1_IO_BASE,
+			       CONFIG_SYS_PCI1_IO_BUS,
 			       CONFIG_SYS_PCI1_IO_PHYS,
 			       CONFIG_SYS_PCI1_IO_SIZE,
 			       PCI_REGION_IO);
 
-#ifdef CONFIG_SYS_PCIE3_MEM_BASE2
+#ifdef CONFIG_SYS_PCIE3_MEM_BUS2
 		/* outbound memory */
 		pci_set_region(r++,
-			       CONFIG_SYS_PCIE3_MEM_BASE2,
+			       CONFIG_SYS_PCIE3_MEM_BUS2,
 			       CONFIG_SYS_PCIE3_MEM_PHYS2,
 			       CONFIG_SYS_PCIE3_MEM_SIZE2,
 			       PCI_REGION_MEM);
diff --git a/board/freescale/mpc8544ds/tlb.c b/board/freescale/mpc8544ds/tlb.c
index c7442b2..d99441b 100644
--- a/board/freescale/mpc8544ds/tlb.c
+++ b/board/freescale/mpc8544ds/tlb.c
@@ -52,21 +52,21 @@ struct fsl_e_tlb_entry tlb_table[] = {
 	 * TLB 1:	1G	Non-cacheable, guarded
 	 * 0x80000000	1G	PCIE  8,9,a,b
 	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE_PHYS, CONFIG_SYS_PCIE_PHYS,
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE_VIRT, CONFIG_SYS_PCIE_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 1, BOOKE_PAGESZ_1G, 1),
 
 	/*
 	 * TLB 2:	256M	Non-cacheable, guarded
 	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCI_PHYS, CONFIG_SYS_PCI_PHYS,
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCI_VIRT, CONFIG_SYS_PCI_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 2, BOOKE_PAGESZ_256M, 1),
 
 	/*
 	 * TLB 3:	256M	Non-cacheable, guarded
 	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCI_PHYS + 0x10000000, CONFIG_SYS_PCI_PHYS + 0x10000000,
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCI_VIRT + 0x10000000, CONFIG_SYS_PCI_PHYS + 0x10000000,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 3, BOOKE_PAGESZ_256M, 1),
 
diff --git a/board/freescale/mpc8548cds/mpc8548cds.c b/board/freescale/mpc8548cds/mpc8548cds.c
index c562fc9..70320ea 100644
--- a/board/freescale/mpc8548cds/mpc8548cds.c
+++ b/board/freescale/mpc8548cds/mpc8548cds.c
@@ -125,7 +125,7 @@ local_bus_init(void)
 	sys_info_t sysinfo;
 
 	get_sys_info(&sysinfo);
-	clkdiv = (lbc->lcrr & 0x0f) * 2;
+	clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2;
 	lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
 
 	gur->lbiuiplldcr1 = 0x00078080;
@@ -306,14 +306,14 @@ pci_init_board(void)
 
 		/* outbound memory */
 		pci_set_region(r++,
-			       CONFIG_SYS_PCI1_MEM_BASE,
+			       CONFIG_SYS_PCI1_MEM_BUS,
 			       CONFIG_SYS_PCI1_MEM_PHYS,
 			       CONFIG_SYS_PCI1_MEM_SIZE,
 			       PCI_REGION_MEM);
 
 		/* outbound io */
 		pci_set_region(r++,
-			       CONFIG_SYS_PCI1_IO_BASE,
+			       CONFIG_SYS_PCI1_IO_BUS,
 			       CONFIG_SYS_PCI1_IO_PHYS,
 			       CONFIG_SYS_PCI1_IO_SIZE,
 			       PCI_REGION_IO);
@@ -390,14 +390,14 @@ pci_init_board(void)
 
 		/* outbound memory */
 		pci_set_region(r++,
-			       CONFIG_SYS_PCIE1_MEM_BASE,
+			       CONFIG_SYS_PCIE1_MEM_BUS,
 			       CONFIG_SYS_PCIE1_MEM_PHYS,
 			       CONFIG_SYS_PCIE1_MEM_SIZE,
 			       PCI_REGION_MEM);
 
 		/* outbound io */
 		pci_set_region(r++,
-			       CONFIG_SYS_PCIE1_IO_BASE,
+			       CONFIG_SYS_PCIE1_IO_BUS,
 			       CONFIG_SYS_PCIE1_IO_PHYS,
 			       CONFIG_SYS_PCIE1_IO_SIZE,
 			       PCI_REGION_IO);
diff --git a/board/freescale/mpc8548cds/tlb.c b/board/freescale/mpc8548cds/tlb.c
index eab212a..2267ad7 100644
--- a/board/freescale/mpc8548cds/tlb.c
+++ b/board/freescale/mpc8548cds/tlb.c
@@ -54,7 +54,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
 	 * TLB 1:	1G	Non-cacheable, guarded
 	 * 0x80000000	1G	PCI1/PCIE  8,9,a,b
 	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCI_PHYS, CONFIG_SYS_PCI_PHYS,
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCI_VIRT, CONFIG_SYS_PCI_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 1, BOOKE_PAGESZ_1G, 1),
 
@@ -62,14 +62,14 @@ struct fsl_e_tlb_entry tlb_table[] = {
 	/*
 	 * TLB 2:	256M	Non-cacheable, guarded
 	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BASE, CONFIG_SYS_RIO_MEM_BASE,
+	SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_VIRT, CONFIG_SYS_RIO_MEM_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 2, BOOKE_PAGESZ_256M, 1),
 
 	/*
 	 * TLB 3:	256M	Non-cacheable, guarded
 	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BASE + 0x10000000, CONFIG_SYS_RIO_MEM_BASE + 0x10000000,
+	SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_VIRT + 0x10000000, CONFIG_SYS_RIO_MEM_PHYS + 0x10000000,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 3, BOOKE_PAGESZ_256M, 1),
 #endif
diff --git a/board/freescale/mpc8555cds/mpc8555cds.c b/board/freescale/mpc8555cds/mpc8555cds.c
index 33685c1..53d5a93 100644
--- a/board/freescale/mpc8555cds/mpc8555cds.c
+++ b/board/freescale/mpc8555cds/mpc8555cds.c
@@ -308,7 +308,7 @@ local_bus_init(void)
 	 */
 
 	get_sys_info(&sysinfo);
-	clkdiv = lbc->lcrr & 0x0f;
+	clkdiv = lbc->lcrr & LCRR_CLKDIV;
 	lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
 
 	if (lbc_hz < 66) {
diff --git a/board/freescale/mpc8555cds/tlb.c b/board/freescale/mpc8555cds/tlb.c
index bf957c0..ae6812f 100644
--- a/board/freescale/mpc8555cds/tlb.c
+++ b/board/freescale/mpc8555cds/tlb.c
@@ -54,7 +54,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
 	 * TLB 1:	256M	Non-cacheable, guarded
 	 * 0x80000000	256M	PCI1 MEM First half
 	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS,
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT, CONFIG_SYS_PCI1_MEM_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 1, BOOKE_PAGESZ_256M, 1),
 
@@ -62,7 +62,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
 	 * TLB 2:	256M	Non-cacheable, guarded
 	 * 0x90000000	256M	PCI1 MEM Second half
 	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000,
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT + 0x10000000, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 2, BOOKE_PAGESZ_256M, 1),
 
@@ -70,7 +70,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
 	 * TLB 3:	256M	Non-cacheable, guarded
 	 * 0xa0000000	256M	PCI2 MEM First half
 	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCI2_MEM_PHYS, CONFIG_SYS_PCI2_MEM_PHYS,
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCI2_MEM_VIRT, CONFIG_SYS_PCI2_MEM_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 3, BOOKE_PAGESZ_256M, 1),
 
@@ -78,7 +78,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
 	 * TLB 4:	256M	Non-cacheable, guarded
 	 * 0xb0000000	256M	PCI2 MEM Second half
 	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCI2_MEM_PHYS + 0x10000000, CONFIG_SYS_PCI2_MEM_PHYS + 0x10000000,
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCI2_MEM_VIRT + 0x10000000, CONFIG_SYS_PCI2_MEM_PHYS + 0x10000000,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 4, BOOKE_PAGESZ_256M, 1),
 
diff --git a/board/freescale/mpc8560ads/ddr.c b/board/freescale/mpc8560ads/ddr.c
index 7850794..93d1100 100644
--- a/board/freescale/mpc8560ads/ddr.c
+++ b/board/freescale/mpc8560ads/ddr.c
@@ -65,6 +65,9 @@ void fsl_ddr_board_options(memctl_options_t *popts,
 	 */
 	popts->write_data_delay = 3;
 
+	/* 2T timing enable */
+	popts->twoT_en = 1;
+
 	/*
 	 * Factors to consider for half-strength driver enable:
 	 *	- number of DIMMs installed
diff --git a/board/freescale/mpc8560ads/law.c b/board/freescale/mpc8560ads/law.c
index 7dd8f29..f5644e1 100644
--- a/board/freescale/mpc8560ads/law.c
+++ b/board/freescale/mpc8560ads/law.c
@@ -52,7 +52,7 @@ struct law_entry law_table[] = {
 	/* This is not so much the SDRAM map as it is the whole localbus map. */
 	SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
 	SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI),
-	SET_LAW(CONFIG_SYS_RIO_MEM_BASE, LAWAR_SIZE_512M, LAW_TRGT_IF_RIO),
+	SET_LAW(CONFIG_SYS_RIO_MEM_PHYS, LAWAR_SIZE_512M, LAW_TRGT_IF_RIO),
 };
 
 int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/mpc8560ads/mpc8560ads.c b/board/freescale/mpc8560ads/mpc8560ads.c
index 3730818..ac7778e 100644
--- a/board/freescale/mpc8560ads/mpc8560ads.c
+++ b/board/freescale/mpc8560ads/mpc8560ads.c
@@ -337,7 +337,7 @@ local_bus_init(void)
 	 */
 
 	get_sys_info(&sysinfo);
-	clkdiv = lbc->lcrr & 0x0f;
+	clkdiv = lbc->lcrr & LCRR_CLKDIV;
 	lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
 
 	if (lbc_hz < 66) {
diff --git a/board/freescale/mpc8560ads/tlb.c b/board/freescale/mpc8560ads/tlb.c
index 2ec3ccc..a9925d5 100644
--- a/board/freescale/mpc8560ads/tlb.c
+++ b/board/freescale/mpc8560ads/tlb.c
@@ -54,7 +54,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
 	 * TLB 1:	256M	Non-cacheable, guarded
 	 * 0x80000000	256M	PCI1 MEM First half
 	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS,
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT, CONFIG_SYS_PCI1_MEM_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 1, BOOKE_PAGESZ_256M, 1),
 
@@ -62,7 +62,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
 	 * TLB 2:	256M	Non-cacheable, guarded
 	 * 0x90000000	256M	PCI1 MEM Second half
 	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000,
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT + 0x10000000, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 2, BOOKE_PAGESZ_256M, 1),
 
@@ -70,7 +70,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
 	 * TLB 3:	256M	Non-cacheable, guarded
 	 * 0xc0000000	256M	Rapid IO MEM First half
 	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BASE, CONFIG_SYS_RIO_MEM_BASE,
+	SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_VIRT, CONFIG_SYS_RIO_MEM_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 3, BOOKE_PAGESZ_256M, 1),
 
@@ -78,7 +78,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
 	 * TLB 4:	256M	Non-cacheable, guarded
 	 * 0xd0000000	256M	Rapid IO MEM Second half
 	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BASE + 0x10000000, CONFIG_SYS_RIO_MEM_BASE + 0x10000000,
+	SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_VIRT + 0x10000000, CONFIG_SYS_RIO_MEM_PHYS + 0x10000000,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 4, BOOKE_PAGESZ_256M, 1),
 
diff --git a/board/freescale/mpc8568mds/law.c b/board/freescale/mpc8568mds/law.c
index da7b6dc..3114e8a 100644
--- a/board/freescale/mpc8568mds/law.c
+++ b/board/freescale/mpc8568mds/law.c
@@ -54,7 +54,7 @@ struct law_entry law_table[] = {
 	SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_1),
 	SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCI),
 	SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCIE_1),
-	SET_LAW(CONFIG_SYS_SRIO_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_RIO),
+	SET_LAW(CONFIG_SYS_SRIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO),
 	/* LBC window - maps 256M.  That's SDRAM, BCSR, PIBs, and Flash */
 	SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
 };
diff --git a/board/freescale/mpc8568mds/mpc8568mds.c b/board/freescale/mpc8568mds/mpc8568mds.c
index bc93be8..915fae7 100644
--- a/board/freescale/mpc8568mds/mpc8568mds.c
+++ b/board/freescale/mpc8568mds/mpc8568mds.c
@@ -188,7 +188,7 @@ local_bus_init(void)
 	sys_info_t sysinfo;
 
 	get_sys_info(&sysinfo);
-	clkdiv = (lbc->lcrr & 0x0f) * 2;
+	clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2;
 	lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
 
 	gur->lbiuiplldcr1 = 0x00078080;
@@ -397,14 +397,14 @@ pci_init_board(void)
 
 		/* outbound memory */
 		pci_set_region(r++,
-				CONFIG_SYS_PCI1_MEM_BASE,
+				CONFIG_SYS_PCI1_MEM_BUS,
 				CONFIG_SYS_PCI1_MEM_PHYS,
 				CONFIG_SYS_PCI1_MEM_SIZE,
 				PCI_REGION_MEM);
 
 		/* outbound io */
 		pci_set_region(r++,
-				CONFIG_SYS_PCI1_IO_BASE,
+				CONFIG_SYS_PCI1_IO_BUS,
 				CONFIG_SYS_PCI1_IO_PHYS,
 				CONFIG_SYS_PCI1_IO_SIZE,
 				PCI_REGION_IO);
@@ -450,14 +450,14 @@ pci_init_board(void)
 
 		/* outbound memory */
 		pci_set_region(r++,
-				CONFIG_SYS_PCIE1_MEM_BASE,
+				CONFIG_SYS_PCIE1_MEM_BUS,
 				CONFIG_SYS_PCIE1_MEM_PHYS,
 				CONFIG_SYS_PCIE1_MEM_SIZE,
 				PCI_REGION_MEM);
 
 		/* outbound io */
 		pci_set_region(r++,
-				CONFIG_SYS_PCIE1_IO_BASE,
+				CONFIG_SYS_PCIE1_IO_BUS,
 				CONFIG_SYS_PCIE1_IO_PHYS,
 				CONFIG_SYS_PCIE1_IO_SIZE,
 				PCI_REGION_IO);
diff --git a/board/freescale/mpc8568mds/tlb.c b/board/freescale/mpc8568mds/tlb.c
index 1077552..8470c87 100644
--- a/board/freescale/mpc8568mds/tlb.c
+++ b/board/freescale/mpc8568mds/tlb.c
@@ -64,7 +64,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
 	 * 0x80000000	512M	PCI1 MEM
 	 * 0xa0000000	512M	PCIe MEM
 	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS,
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT, CONFIG_SYS_PCI1_MEM_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 2, BOOKE_PAGESZ_1G, 1),
 
diff --git a/board/freescale/mpc8572ds/law.c b/board/freescale/mpc8572ds/law.c
index 83eb681..02ea0ec 100644
--- a/board/freescale/mpc8572ds/law.c
+++ b/board/freescale/mpc8572ds/law.c
@@ -28,14 +28,14 @@
 #include <asm/mmu.h>
 
 struct law_entry law_table[] = {
-	SET_LAW(CONFIG_SYS_FLASH_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
+	SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
 	SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAWAR_SIZE_512M, LAW_TRGT_IF_PCIE_1),
 	SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_1),
 	SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAWAR_SIZE_512M, LAW_TRGT_IF_PCIE_2),
 	SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_2),
 	SET_LAW(CONFIG_SYS_PCIE3_MEM_PHYS, LAWAR_SIZE_512M, LAW_TRGT_IF_PCIE_3),
 	SET_LAW(CONFIG_SYS_PCIE3_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_3),
-	SET_LAW(PIXIS_BASE, LAW_SIZE_4K, LAW_TRGT_IF_LBC),
+	SET_LAW(PIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_LBC),
 	SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
 };
 
diff --git a/board/freescale/mpc8572ds/mpc8572ds.c b/board/freescale/mpc8572ds/mpc8572ds.c
index a14db5a..e57f9ff 100644
--- a/board/freescale/mpc8572ds/mpc8572ds.c
+++ b/board/freescale/mpc8572ds/mpc8572ds.c
@@ -166,11 +166,11 @@ void pci_init_board(void)
 		struct pci_controller *hose = &pcie3_hose;
 		int pcie_ep = (host_agent == 0) || (host_agent == 3) ||
 			(host_agent == 5) || (host_agent == 6);
-		int pcie_configured  = io_sel >= 1;
+		int pcie_configured  = (io_sel == 0x7);
 		struct pci_region *r = hose->regions;
 		u32 temp32;
 
-		if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
+		if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)){
 			printf ("\n    PCIE3 connected to ULI as %s (base address %x)",
 					pcie_ep ? "End Point" : "Root Complex",
 					(uint)pci);
@@ -185,14 +185,14 @@ void pci_init_board(void)
 
 			/* outbound memory */
 			pci_set_region(r++,
-					CONFIG_SYS_PCIE3_MEM_BASE,
+					CONFIG_SYS_PCIE3_MEM_BUS,
 					CONFIG_SYS_PCIE3_MEM_PHYS,
 					CONFIG_SYS_PCIE3_MEM_SIZE,
 					PCI_REGION_MEM);
 
 			/* outbound io */
 			pci_set_region(r++,
-					CONFIG_SYS_PCIE3_IO_BASE,
+					CONFIG_SYS_PCIE3_IO_BUS,
 					CONFIG_SYS_PCIE3_IO_PHYS,
 					CONFIG_SYS_PCIE3_IO_SIZE,
 					PCI_REGION_IO);
@@ -215,7 +215,7 @@ void pci_init_board(void)
 
 			pci_hose_read_config_dword(hose, PCI_BDF(2, 0x1d, 0 ),
 					PCI_BASE_ADDRESS_1, &temp32);
-			if (temp32 >= CONFIG_SYS_PCIE3_MEM_PHYS) {
+			if (temp32 >= CONFIG_SYS_PCIE3_MEM_BUS) {
 				debug(" uli1572 read to %x\n", temp32);
 				in_be32((unsigned *)temp32);
 			}
@@ -234,10 +234,10 @@ void pci_init_board(void)
 		struct pci_controller *hose = &pcie2_hose;
 		int pcie_ep = (host_agent == 2) || (host_agent == 4) ||
 			(host_agent == 6) || (host_agent == 0);
-		int pcie_configured  = io_sel & 4;
+		int pcie_configured  = (io_sel == 0x3) || (io_sel == 0x7);
 		struct pci_region *r = hose->regions;
 
-		if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
+		if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE2)){
 			printf ("\n    PCIE2 connected to Slot 1 as %s (base address %x)",
 					pcie_ep ? "End Point" : "Root Complex",
 					(uint)pci);
@@ -252,14 +252,14 @@ void pci_init_board(void)
 
 			/* outbound memory */
 			pci_set_region(r++,
-					CONFIG_SYS_PCIE2_MEM_BASE,
+					CONFIG_SYS_PCIE2_MEM_BUS,
 					CONFIG_SYS_PCIE2_MEM_PHYS,
 					CONFIG_SYS_PCIE2_MEM_SIZE,
 					PCI_REGION_MEM);
 
 			/* outbound io */
 			pci_set_region(r++,
-					CONFIG_SYS_PCIE2_IO_BASE,
+					CONFIG_SYS_PCIE2_IO_BUS,
 					CONFIG_SYS_PCIE2_IO_PHYS,
 					CONFIG_SYS_PCIE2_IO_SIZE,
 					PCI_REGION_IO);
@@ -287,7 +287,9 @@ void pci_init_board(void)
 		struct pci_controller *hose = &pcie1_hose;
 		int pcie_ep = (host_agent <= 1) || (host_agent == 4) ||
 			(host_agent == 5);
-		int pcie_configured  = io_sel & 6;
+		int pcie_configured  = (io_sel == 0x2) || (io_sel == 0x3) ||
+					(io_sel == 0x7) || (io_sel == 0xb) ||
+					(io_sel == 0xc) || (io_sel == 0xf);
 		struct pci_region *r = hose->regions;
 
 		if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
@@ -305,14 +307,14 @@ void pci_init_board(void)
 
 			/* outbound memory */
 			pci_set_region(r++,
-					CONFIG_SYS_PCIE1_MEM_BASE,
+					CONFIG_SYS_PCIE1_MEM_BUS,
 					CONFIG_SYS_PCIE1_MEM_PHYS,
 					CONFIG_SYS_PCIE1_MEM_SIZE,
 					PCI_REGION_MEM);
 
 			/* outbound io */
 			pci_set_region(r++,
-					CONFIG_SYS_PCIE1_IO_BASE,
+					CONFIG_SYS_PCIE1_IO_BUS,
 					CONFIG_SYS_PCIE1_IO_PHYS,
 					CONFIG_SYS_PCIE1_IO_SIZE,
 					PCI_REGION_IO);
@@ -356,7 +358,7 @@ int board_early_init_r(void)
 	/* invalidate existing TLB entry for flash + promjet */
 	disable_tlb(flash_esel);
 
-	set_tlb(1, flashbase, flashbase,		/* tlb, epn, rpn */
+	set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,	/* tlb, epn, rpn */
 			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,	/* perms, wimge */
 			0, flash_esel, BOOKE_PAGESZ_256M, 1);	/* ts, esel, tsize, iprot */
 
diff --git a/board/freescale/mpc8572ds/tlb.c b/board/freescale/mpc8572ds/tlb.c
index 8d1f646..d832f89 100644
--- a/board/freescale/mpc8572ds/tlb.c
+++ b/board/freescale/mpc8572ds/tlb.c
@@ -41,10 +41,6 @@ struct fsl_e_tlb_entry tlb_table[] = {
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 0, BOOKE_PAGESZ_4K, 0),
 
-	SET_TLB_ENTRY(0, PIXIS_BASE, PIXIS_BASE,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 0, BOOKE_PAGESZ_4K, 0),
-
 	/* TLB 1 */
 	/* *I*** - Covers boot page */
 	SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
@@ -58,26 +54,26 @@ struct fsl_e_tlb_entry tlb_table[] = {
 
 	/* W**G* - Flash/promjet, localbus */
 	/* This will be changed to *I*G* after relocation to RAM. */
-	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE,
+	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
 		      MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
 		      0, 2, BOOKE_PAGESZ_256M, 1),
 
 	/* *I*G* - PCI */
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_PHYS, CONFIG_SYS_PCIE3_MEM_PHYS,
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 3, BOOKE_PAGESZ_1G, 1),
 
 	/* *I*G* - PCI */
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_PHYS + 0x40000000, CONFIG_SYS_PCIE3_MEM_PHYS + 0x40000000,
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x40000000, CONFIG_SYS_PCIE3_MEM_PHYS + 0x40000000,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 4, BOOKE_PAGESZ_256M, 1),
 
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_PHYS + 0x50000000, CONFIG_SYS_PCIE3_MEM_PHYS + 0x50000000,
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x50000000, CONFIG_SYS_PCIE3_MEM_PHYS + 0x50000000,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 5, BOOKE_PAGESZ_256M, 1),
 
 	/* *I*G* - PCI I/O */
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_IO_PHYS, CONFIG_SYS_PCIE3_IO_PHYS,
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_IO_VIRT, CONFIG_SYS_PCIE3_IO_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 6, BOOKE_PAGESZ_256K, 1),
 
@@ -86,6 +82,9 @@ struct fsl_e_tlb_entry tlb_table[] = {
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 7, BOOKE_PAGESZ_1M, 1),
 
+	SET_TLB_ENTRY(1, PIXIS_BASE, PIXIS_BASE_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 8, BOOKE_PAGESZ_4K, 1),
 };
 
 int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/board/freescale/mpc8610hpcd/ddr.c b/board/freescale/mpc8610hpcd/ddr.c
index 414ac24..0117d13 100644
--- a/board/freescale/mpc8610hpcd/ddr.c
+++ b/board/freescale/mpc8610hpcd/ddr.c
@@ -74,6 +74,9 @@ void fsl_ddr_board_options(memctl_options_t *popts,
 	 */
 	popts->write_data_delay = 3;
 
+	/* 2T timing enable */
+	popts->twoT_en = 1;
+
 	/*
 	 * Factors to consider for half-strength driver enable:
 	 *	- number of DIMMs installed
diff --git a/board/freescale/mpc8610hpcd/law.c b/board/freescale/mpc8610hpcd/law.c
index 2aad28a..0fc8384 100644
--- a/board/freescale/mpc8610hpcd/law.c
+++ b/board/freescale/mpc8610hpcd/law.c
@@ -31,8 +31,8 @@ struct law_entry law_table[] = {
 #if !defined(CONFIG_SPD_EEPROM)
 	SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_DDR_1),
 #endif
-	SET_LAW(CONFIG_SYS_PCIE1_MEM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_1),
-	SET_LAW(CONFIG_SYS_PCIE2_MEM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_2),
+	SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_1),
+	SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_2),
 	SET_LAW(PIXIS_BASE, LAW_SIZE_2M, LAW_TRGT_IF_LBC),
 	SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCIE_1),
 	SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCIE_2),
diff --git a/board/freescale/mpc8610hpcd/mpc8610hpcd.c b/board/freescale/mpc8610hpcd/mpc8610hpcd.c
index 2792778..a2097a5 100644
--- a/board/freescale/mpc8610hpcd/mpc8610hpcd.c
+++ b/board/freescale/mpc8610hpcd/mpc8610hpcd.c
@@ -266,14 +266,14 @@ void pci_init_board(void)
 
 		/* outbound memory */
 		pci_set_region(r++,
-			 CONFIG_SYS_PCIE1_MEM_BASE,
+			 CONFIG_SYS_PCIE1_MEM_BUS,
 			 CONFIG_SYS_PCIE1_MEM_PHYS,
 			 CONFIG_SYS_PCIE1_MEM_SIZE,
 			 PCI_REGION_MEM);
 
 		/* outbound io */
 		pci_set_region(r++,
-			 CONFIG_SYS_PCIE1_IO_BASE,
+			 CONFIG_SYS_PCIE1_IO_BUS,
 			 CONFIG_SYS_PCIE1_IO_PHYS,
 			 CONFIG_SYS_PCIE1_IO_SIZE,
 			 PCI_REGION_IO);
@@ -321,14 +321,14 @@ void pci_init_board(void)
 
 		/* outbound memory */
 		pci_set_region(r++,
-			 CONFIG_SYS_PCIE2_MEM_BASE,
+			 CONFIG_SYS_PCIE2_MEM_BUS,
 			 CONFIG_SYS_PCIE2_MEM_PHYS,
 			 CONFIG_SYS_PCIE2_MEM_SIZE,
 			 PCI_REGION_MEM);
 
 		/* outbound io */
 		pci_set_region(r++,
-			 CONFIG_SYS_PCIE2_IO_BASE,
+			 CONFIG_SYS_PCIE2_IO_BUS,
 			 CONFIG_SYS_PCIE2_IO_PHYS,
 			 CONFIG_SYS_PCIE2_IO_SIZE,
 			 PCI_REGION_IO);
@@ -370,14 +370,14 @@ void pci_init_board(void)
 
 		/* outbound memory */
 		pci_set_region(r++,
-			 CONFIG_SYS_PCI1_MEM_BASE,
+			 CONFIG_SYS_PCI1_MEM_BUS,
 			 CONFIG_SYS_PCI1_MEM_PHYS,
 			 CONFIG_SYS_PCI1_MEM_SIZE,
 			 PCI_REGION_MEM);
 
 		/* outbound io */
 		pci_set_region(r++,
-			 CONFIG_SYS_PCI1_IO_BASE,
+			 CONFIG_SYS_PCI1_IO_BUS,
 			 CONFIG_SYS_PCI1_IO_PHYS,
 			 CONFIG_SYS_PCI1_IO_SIZE,
 			 PCI_REGION_IO);
diff --git a/board/freescale/mpc8641hpcn/ddr.c b/board/freescale/mpc8641hpcn/ddr.c
index 3789b54..8dc249b 100644
--- a/board/freescale/mpc8641hpcn/ddr.c
+++ b/board/freescale/mpc8641hpcn/ddr.c
@@ -162,4 +162,6 @@ void fsl_ddr_board_options(memctl_options_t *popts,
 		}
 	}
 
+	/* 2T timing enable */
+	popts->twoT_en = 1;
 }