armv8: ls1012a: Add support of ls1012afrdm board

QorIQ LS1012A FREEDOM (LS1012AFRDM) is a high-performance
development platform, with a complete debugging environment.
The LS1012AFRDM board supports the QorIQ LS1012A processor and is
optimized to support the high-bandwidth DDR3L memory and
a full complement of high-speed SerDes ports.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

5 files changed, 278 insertions, 0 deletions

diff --git a/board/freescale/ls1012afrdm/Kconfig b/board/freescale/ls1012afrdm/Kconfig
new file mode 100644
index 0000000..a34521c
--- /dev/null
+++ b/board/freescale/ls1012afrdm/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_LS1012AFRDM
+
+config SYS_BOARD
+	default "ls1012afrdm"
+
+config SYS_VENDOR
+	default "freescale"
+
+config SYS_SOC
+	default "fsl-layerscape"
+
+config SYS_CONFIG_NAME
+	default "ls1012afrdm"
+
+endif
diff --git a/board/freescale/ls1012afrdm/MAINTAINERS b/board/freescale/ls1012afrdm/MAINTAINERS
new file mode 100644
index 0000000..842f86f
--- /dev/null
+++ b/board/freescale/ls1012afrdm/MAINTAINERS
@@ -0,0 +1,6 @@
+LS1012AFRDM BOARD
+M:	Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
+S:	Maintained
+F:	board/freescale/ls1012afrdm/
+F:	include/configs/ls1012afrdm.h
+F:	configs/ls1012afrdm_qspi_defconfig
diff --git a/board/freescale/ls1012afrdm/Makefile b/board/freescale/ls1012afrdm/Makefile
new file mode 100644
index 0000000..dbfa2ce
--- /dev/null
+++ b/board/freescale/ls1012afrdm/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright 2016 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier:      GPL-2.0+
+#
+
+obj-y += ls1012afrdm.o
diff --git a/board/freescale/ls1012afrdm/README b/board/freescale/ls1012afrdm/README
new file mode 100644
index 0000000..181c461
--- /dev/null
+++ b/board/freescale/ls1012afrdm/README
@@ -0,0 +1,58 @@
+Overview
+--------
+QorIQ LS1012A FREEDOM (LS1012AFRDM) is a high-performance development
+platform, with a complete debugging environment. The LS1012AFRDM board
+supports the QorIQ LS1012A processor and is optimized to support the
+high-bandwidth DDR3L memory and a full complement of high-speed SerDes ports.
+
+LS1012A SoC Overview
+--------------------
+Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS2080A
+SoC overview.
+
+ LS1012AFRDM board Overview
+ -----------------------
+ - SERDES Connections, 2 lanes supportingspeeds upto 1 Gbit/s
+     - 2 SGMII 1G PHYs
+ - DDR Controller
+     - 4 Gb DDR3L SDRAM memory, running at data rates up to 1 GT/s
+	operating at 1.35 V
+ - QSPI
+     - Onboard 512 Mbit QSPI flash memory running at speed up
+      to 108/54 MHz
+ - One high-speed USB 2.0/3.0 port, one USB 2.0 port
+     - USB 2.0/3.0 port is configured as On-The-Go (OTG) with a
+       Micro-AB connector.
+     - USB 2.0 port is a debug port (CMSIS DAP) and is configured
+       as a Micro-AB device.
+ - I2C controller
+     - One I2C bus with connectivity to Arduino headers
+ - UART
+     - UART (Console): UART1 (Without flow control) for console
+ - ARM JTAG support
+     - ARM Cortex® 10-pin JTAG connector for LS1012A
+     - CMSIS DAP through K20 microcontroller
+ - SAI Audio interface
+     - One SAI port, SAI 2 with full duplex support
+ - Clocks
+     - 25 MHz crystal for LS1012A
+     - 8 MHz Crystal for K20
+     - 24 MHz for SC16IS740IPW SPI to Dual UART bridge
+ - Power Supplies
+     - 5 V input supply from USB
+     - 0.9 V, 1.35 V, and 1.8 V for VDD/Core, DDR, I/O, and
+       other board interfaces
+
+Booting Options
+---------------
+QSPI Flash 1
+
+QSPI flash map
+--------------
+Images		| Size	|QSPI Flash Address
+------------------------------------------
+RCW + PBI	| 1MB	| 0x4000_0000
+U-boot 		| 1MB	| 0x4010_0000
+U-boot Env 	| 1MB	| 0x4020_0000
+PPA FIT image	| 2MB	| 0x4050_0000
+Linux ITB	| ~53MB | 0x40A0_0000
diff --git a/board/freescale/ls1012afrdm/ls1012afrdm.c b/board/freescale/ls1012afrdm/ls1012afrdm.c
new file mode 100644
index 0000000..a94a458
--- /dev/null
+++ b/board/freescale/ls1012afrdm/ls1012afrdm.c
@@ -0,0 +1,192 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/fsl_serdes.h>
+#include <asm/arch/soc.h>
+#include <hwconfig.h>
+#include <fsl_csu.h>
+#include <environment.h>
+#include <fsl_mmdc.h>
+#include <netdev.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void set_wait_for_bits_clear(void *ptr, u32 value, u32 bits)
+{
+	int timeout = 1000;
+
+	out_be32(ptr, value);
+
+	while (in_be32(ptr) & bits) {
+		udelay(100);
+		timeout--;
+	}
+	if (timeout <= 0)
+		puts("Error: wait for clear timeout.\n");
+}
+
+int checkboard(void)
+{
+	puts("Board: LS1012AFRDM ");
+
+	return 0;
+}
+
+void mmdc_init(void)
+{
+	struct mmdc_p_regs *mmdc =
+		(struct mmdc_p_regs *)CONFIG_SYS_FSL_DDR_ADDR;
+
+	out_be32(&mmdc->mdscr, CONFIGURATION_REQ);
+
+	/* configure timing parms */
+	out_be32(&mmdc->mdotc,  CONFIG_SYS_MMDC_CORE_ODT_TIMING);
+	out_be32(&mmdc->mdcfg0, CONFIG_SYS_MMDC_CORE_TIMING_CFG_0);
+	out_be32(&mmdc->mdcfg1, CONFIG_SYS_MMDC_CORE_TIMING_CFG_1);
+	out_be32(&mmdc->mdcfg2, CONFIG_SYS_MMDC_CORE_TIMING_CFG_2);
+
+	/* other parms	*/
+	out_be32(&mmdc->mdmisc,    CONFIG_SYS_MMDC_CORE_MISC);
+	out_be32(&mmdc->mpmur0,    CONFIG_SYS_MMDC_PHY_MEASURE_UNIT);
+	out_be32(&mmdc->mdrwd,     CONFIG_SYS_MMDC_CORE_RDWR_CMD_DELAY);
+	out_be32(&mmdc->mpodtctrl, CONFIG_SYS_MMDC_PHY_ODT_CTRL);
+
+	/* out of reset delays */
+	out_be32(&mmdc->mdor,  CONFIG_SYS_MMDC_CORE_OUT_OF_RESET_DELAY);
+
+	/* physical parms */
+	out_be32(&mmdc->mdctl, CONFIG_SYS_MMDC_CORE_CONTROL_1);
+	out_be32(&mmdc->mdasp, CONFIG_SYS_MMDC_CORE_ADDR_PARTITION);
+
+       /* Enable MMDC */
+	out_be32(&mmdc->mdctl, CONFIG_SYS_MMDC_CORE_CONTROL_2);
+
+	/* dram init sequence: update MRs */
+	out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x8) | CONFIGURATION_REQ |
+				CMD_LOAD_MODE_REG | CMD_BANK_ADDR_2));
+	out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
+				CMD_BANK_ADDR_3));
+	out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
+				CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1));
+	out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x19) |
+				CMD_ADDR_LSB_MR_ADDR(0x30) | CONFIGURATION_REQ |
+				CMD_LOAD_MODE_REG | CMD_BANK_ADDR_0));
+
+       /* dram init sequence: ZQCL */
+	out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ |
+				CMD_ZQ_CALIBRATION | CMD_BANK_ADDR_0));
+	set_wait_for_bits_clear(&mmdc->mpzqhwctrl,
+				CONFIG_SYS_MMDC_PHY_ZQ_HW_CTRL,
+				FORCE_ZQ_AUTO_CALIBRATION);
+
+       /* Calibrations now: wr lvl */
+	out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x84) |
+				CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
+				CMD_BANK_ADDR_1));
+	out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | WL_EN | CMD_NORMAL));
+	set_wait_for_bits_clear(&mmdc->mpwlgcr, WR_LVL_HW_EN, WR_LVL_HW_EN);
+
+	mdelay(1);
+
+	out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
+				CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1));
+	out_be32(&mmdc->mdscr, CONFIGURATION_REQ);
+
+	mdelay(1);
+
+       /* Calibrations now: Read DQS gating calibration */
+	out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ |
+				CMD_PRECHARGE_BANK_OPEN | CMD_BANK_ADDR_0));
+	out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
+				CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3));
+	out_be32(&mmdc->mppdcmpr2, MPR_COMPARE_EN);
+	out_be32(&mmdc->mprddlctl, CONFIG_SYS_MMDC_PHY_RD_DLY_LINES_CFG);
+	set_wait_for_bits_clear(&mmdc->mpdgctrl0,
+				AUTO_RD_DQS_GATING_CALIBRATION_EN,
+				AUTO_RD_DQS_GATING_CALIBRATION_EN);
+
+	out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
+				CMD_BANK_ADDR_3));
+
+       /* Calibrations now: Read calibration */
+	out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ |
+				CMD_PRECHARGE_BANK_OPEN | CMD_BANK_ADDR_0));
+	out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
+				CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3));
+	out_be32(&mmdc->mppdcmpr2,  MPR_COMPARE_EN);
+	set_wait_for_bits_clear(&mmdc->mprddlhwctl,
+				AUTO_RD_CALIBRATION_EN,
+				AUTO_RD_CALIBRATION_EN);
+
+	out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
+				CMD_BANK_ADDR_3));
+
+       /* PD, SR */
+	out_be32(&mmdc->mdpdc, CONFIG_SYS_MMDC_CORE_PWR_DOWN_CTRL);
+	out_be32(&mmdc->mapsr, CONFIG_SYS_MMDC_CORE_PWR_SAV_CTRL_STAT);
+
+       /* refresh scheme */
+	set_wait_for_bits_clear(&mmdc->mdref,
+				CONFIG_SYS_MMDC_CORE_REFRESH_CTL,
+				START_REFRESH);
+
+       /* disable CON_REQ */
+	out_be32(&mmdc->mdscr, DISABLE_CFG_REQ);
+}
+
+int dram_init(void)
+{
+	mmdc_init();
+
+	gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+
+	return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+	return pci_eth_init(bis);
+}
+
+int board_early_init_f(void)
+{
+	fsl_lsch2_early_init_f();
+
+	return 0;
+}
+
+int board_init(void)
+{
+	struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
+	/*
+	 * Set CCI-400 control override register to enable barrier
+	 * transaction
+	 */
+	out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
+
+#ifdef CONFIG_ENV_IS_NOWHERE
+	gd->env_addr = (ulong)&default_environment[0];
+#endif
+
+#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
+	enable_layerscape_ns_access();
+#endif
+
+	return 0;
+}
+
+int ft_board_setup(void *blob, bd_t *bd)
+{
+	arch_fixup_fdt(blob);
+
+	ft_cpu_setup(blob, bd);
+
+	return 0;
+}