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| author | Dipen Dudhat <dipen.dudhat@freescale.com> | 2009-10-08 13:33:18 +0530 |
|---|---|---|
| committer | Kumar Gala <galak@kernel.crashing.org> | 2009-10-16 10:21:39 -0500 |
| commit | f7780ec977e545b83bc5068e0957d640f1d98f13 (patch) | |
| tree | 9a63f9a66c4c66e2a23c85bbc94c29d9c10bc789 /board/freescale | |
| parent | d11823ca3cb551814ffcd926402c8bcf3a7eff35 (diff) | |
| download | u-boot-imx-f7780ec977e545b83bc5068e0957d640f1d98f13.zip u-boot-imx-f7780ec977e545b83bc5068e0957d640f1d98f13.tar.gz u-boot-imx-f7780ec977e545b83bc5068e0957d640f1d98f13.tar.bz2 | |
ppc/P1_P2_RDB: NAND Boot Support
NAND Boot support for P1 and P2 series RDB platforms.
This patch is derived from NAND Boot support on MPC8536DS.
Signed-off-by: Dipen Dudhat <dipen.dudhat@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'board/freescale')
| -rw-r--r-- | board/freescale/p1_p2_rdb/config.mk | 7 | ||||
| -rw-r--r-- | board/freescale/p1_p2_rdb/tlb.c | 10 |
2 files changed, 17 insertions, 0 deletions
diff --git a/board/freescale/p1_p2_rdb/config.mk b/board/freescale/p1_p2_rdb/config.mk index a56b536..17abcf8 100644 --- a/board/freescale/p1_p2_rdb/config.mk +++ b/board/freescale/p1_p2_rdb/config.mk @@ -24,6 +24,13 @@ # p1_p2rdb board # +ifndef NAND_SPL +ifeq ($(CONFIG_MK_NAND), y) +TEXT_BASE = $(CONFIG_RAMBOOT_TEXT_BASE) +LDSCRIPT := $(TOPDIR)/cpu/$(CPU)/u-boot-nand.lds +endif +endif + ifndef TEXT_BASE TEXT_BASE = 0xeff80000 endif diff --git a/board/freescale/p1_p2_rdb/tlb.c b/board/freescale/p1_p2_rdb/tlb.c index cf9bffe..0009913 100644 --- a/board/freescale/p1_p2_rdb/tlb.c +++ b/board/freescale/p1_p2_rdb/tlb.c @@ -78,6 +78,16 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 6, BOOKE_PAGESZ_1M, 1), +#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR) + /* *I*G - L2SRAM */ + SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 7, BOOKE_PAGESZ_256K, 1), + SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x40000, + CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x40000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 8, BOOKE_PAGESZ_256K, 1), +#endif }; int num_tlb_entries = ARRAY_SIZE(tlb_table); |