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| author | Robby Cai <robby.cai@nxp.com> | 2016-11-30 22:05:03 +0800 |
|---|---|---|
| committer | Ye Li <ye.li@nxp.com> | 2017-06-20 05:50:16 -0500 |
| commit | ed4a8ca872eda7442f5832ecfec7b0da255bb2b6 (patch) | |
| tree | 287c53dce18fe1e050b4bc61f07a483ed5eb858f /board/freescale | |
| parent | 0ff4f6ea8ff753154e4c3c3d7c2bb41d975a2c79 (diff) | |
| download | u-boot-imx-ed4a8ca872eda7442f5832ecfec7b0da255bb2b6.zip u-boot-imx-ed4a8ca872eda7442f5832ecfec7b0da255bb2b6.tar.gz u-boot-imx-ed4a8ca872eda7442f5832ecfec7b0da255bb2b6.tar.bz2 | |
MLK-13723 imx7d: restore epdc QoS setting after exit the lpsr mode
without this patch, the QoS setting will be lost after exit LPSR mode.
The patch moves the QoS setting into DDR setting group (in plugin mode), thus
when exit LPSR mode, QoS setting will be restored as well as DDR setting.
Signed-off-by: Robby Cai <robby.cai@nxp.com>
(cherry picked from commit 0b217456375bace3fbe9a72c7e92a46dc1907277)
(cherry picked from commit 75790929c674eea2f867b86a7734127d4cd45dfc)
Diffstat (limited to 'board/freescale')
| -rw-r--r-- | board/freescale/mx7d_12x12_lpddr3_arm2/plugin.S | 53 |
1 files changed, 53 insertions, 0 deletions
diff --git a/board/freescale/mx7d_12x12_lpddr3_arm2/plugin.S b/board/freescale/mx7d_12x12_lpddr3_arm2/plugin.S index 0c1db98..25eda85 100644 --- a/board/freescale/mx7d_12x12_lpddr3_arm2/plugin.S +++ b/board/freescale/mx7d_12x12_lpddr3_arm2/plugin.S @@ -414,6 +414,8 @@ TUNE_END: cmp r7, #0x1 bne 15b + imx7_qos_setting + /* enable port */ ldr r7, =0x1 str r7, [r3, #0x490] @@ -588,6 +590,57 @@ wait_stat: .endm .macro imx7_qos_setting + ldr r0, =REGS_QOS_BASE + ldr r1, =0 + str r1, [r0, #0] + + ldr r1, =0 + str r1, [r0, #0x60] + + ldr r0, =REGS_QOS_EPDC + ldr r1, =0 + str r1, [r0, #0] + + ldr r0, =REGS_QOS_PXP0 + ldr r1, =0 + str r1, [r0, #0] + + ldr r0, =REGS_QOS_PXP1 + ldr r1, =0 + str r1, [r0, #0] + + ldr r0, =REGS_QOS_EPDC + ldr r1, =0x0f020f22 + str r1, [r0, #0xd0] + str r1, [r0, #0xe0] + + ldr r0, =REGS_QOS_PXP0 + ldr r1, =0x1 + str r1, [r0, #0] + ldr r0, =REGS_QOS_PXP1 + str r1, [r0, #0] + + ldr r0, =REGS_QOS_PXP0 + ldr r1, =0x0f020222 + str r1, [r0, #0x50] + ldr r0, =REGS_QOS_PXP1 + str r1, [r0, #0x50] + + ldr r0, =REGS_QOS_PXP0 + ldr r1, =0x0f020222 + str r1, [r0, #0x60] + ldr r0, =REGS_QOS_PXP1 + str r1, [r0, #0x60] + + ldr r0, =REGS_QOS_PXP0 + ldr r1, =0x0f020422 + str r1, [r0, #0x70] + ldr r0, =REGS_QOS_PXP1 + str r1, [r0, #0x70] + + ldr r0, =IOMUXC_GPR_BASE_ADDR + ldr r1, =0xe080 + str r1, [r0, #0x34] .endm .macro imx7_ddr_setting |