MXSCM-290-1 mx6dqscm: add mx6dqscm boards code

Move the scm mx6dqscm board generic support code from v2016.03
as the base for converting to use DTB OF_CONTROL.

Signed-off-by: Juan Gutierrez <juan.gutierrez@nxp.com>

7 files changed, 2569 insertions, 0 deletions

diff --git a/board/freescale/mx6dqscm/Kconfig b/board/freescale/mx6dqscm/Kconfig
new file mode 100644
index 0000000..d852d1e
--- /dev/null
+++ b/board/freescale/mx6dqscm/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_MX6DQSCM
+
+config SYS_BOARD
+	default "mx6dqscm"
+
+config SYS_VENDOR
+	default "freescale"
+
+config SYS_SOC
+	default "mx6"
+
+config SYS_CONFIG_NAME
+	default "mx6dqscm"
+
+endif
diff --git a/board/freescale/mx6dqscm/MAINTAINERS b/board/freescale/mx6dqscm/MAINTAINERS
new file mode 100644
index 0000000..31bd57d
--- /dev/null
+++ b/board/freescale/mx6dqscm/MAINTAINERS
@@ -0,0 +1,11 @@
+MX6DQSCM BOARDS
+M:	Alejandro Sierra <alejandro.sierra@nxp.com>
+M:	Juan Gutierrez <juan.gutierrez@nxp.com>
+S:	Maintained
+F:	board/freescale/mx6dqscm/
+F:	include/configs/mx6dqscm.h
+F:	configs/mx6dqscm_1gb_fix_evb_defconfig
+F:	configs/mx6dqscm_1gb_fix_qwks_rev2_defconfig
+F:	configs/mx6dqscm_1gb_fix_qwks_rev2_spinor_defconfig
+F:	configs/mx6dqscm_1gb_interleaving_evb_android_defconfig
+F:	configs/mx6dqscm_1gb_interleaving_qwks_rev2_android_defconfig
diff --git a/board/freescale/mx6dqscm/Makefile b/board/freescale/mx6dqscm/Makefile
new file mode 100644
index 0000000..5b8fb46
--- /dev/null
+++ b/board/freescale/mx6dqscm/Makefile
@@ -0,0 +1,11 @@
+#
+# (C) Copyright 2016 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier:  GPL-2.0+
+#
+
+obj-y  := mx6dqscm.o
+
+extra-$(CONFIG_USE_PLUGIN) :=  plugin.bin
+$(obj)/plugin.bin: $(obj)/plugin.o
+	$(OBJCOPY) -O binary --gap-fill 0xff $< $@
diff --git a/board/freescale/mx6dqscm/README b/board/freescale/mx6dqscm/README
new file mode 100644
index 0000000..7dec852
--- /dev/null
+++ b/board/freescale/mx6dqscm/README
@@ -0,0 +1,89 @@
+How to use U-Boot on Freescale MX6DQSCM boards
+----------------------------------------------
+
+- Build U-Boot for MX6DQSCM QWKS rev2 board*:
+
+$ make mx6dqscm_1gb_fix_qwks_rev2_defconfig
+$ make
+
+This will generate the u-boot image u-boot.imx.
+
+- Flash the u-boot image into the micro SD card:
+
+sudo dd if=u-boot.imx of=/dev/sdX bs=1k seek=1; sync
+
+*Other defconfigs availabe are:
+    mx6dqscm_1gb_fix_qwks_rev2_defconfig
+    mx6dqscm_1gb_fix_qwks_rev2_spinor_defconfig
+    mx6dqscm_1gb_interleaving_qwks_rev2_android_defconfig
+
+
+- Jumper settings for fix mode images to boot from the top SD:
+
+Fix mode                        SW1: ON  ON  OFF OFF ON  OFF OFF ON
+Interleave mode                 SW1: ON  OFF ON  OFF ON  OFF OFF ON
+Single channel(512MB/epop)      SW1: ON  OFF OFF OFF ON  OFF OFF ON
+
+- Jumper settings for fix mode images to boot from internal SPI-NOR:
+
+Fix mode                        SW1: ON  ON  OFF X   X   ON  ON  OFF
+Interleave mode                 SW1: ON  OFF ON  X   X   ON  ON  OFF
+Single channel(512MB/epop)      SW1: ON  OFF OFF X   X   ON  ON  OFF
+
+- Jumper settings to boot from internal eMMC (just for ePOP):
+
+Single channel(epop)            SW1: ON  OFF OFF ON  ON  OFF ON  ON
+
+
+Additional configurations
+==========================
+
+For custom configurations like 2GB or 512MB, the CONFIG_SYS_EXTRA_OPTIONS option on the defconfig
+file can be modified according to the customization needed.
+
+Here are some examples for some combinations among the different supported options:
+
+ - memory size option: 512MB, 1GB, 2GB
+ - memeory mode: fix, interleave or single(only for 512MB)
+ - boot mode: SPI-NOR boot or SD
+ - board: evb, qwks
+
+
+512mb qwks-rev2:
+----------------
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6dqscm/imximage_scm_lpddr2.cfg,MX6Q,DDR_MB=512,SYS_USE_SPINOR,DEFAULT_FDT_FILE=\"imx6dqscm-512mb-qwks-rev2-ldo.dtb\",SCM_LPDDR2_512MB"
+
+
+512mb qwks-rev2 spinor-boot:
+----------------------------
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6dqscm/imximage_scm_lpddr2.cfg,MX6Q,DDR_MB=512,SYS_BOOT_SPINOR,DEFAULT_FDT_FILE=\"imx6dqscm-512mb-qwks-rev2-ldo.dtb\",SCM_LPDDR2_512MB"
+
+
+2gb fix evb:
+------------
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6dqscm/imximage_scm_lpddr2.cfg,MX6Q,DDR_MB=2048,SYS_USE_SPINOR,DEFAULT_FDT_FILE=\"imx6dqscm-2gb-evb-fix-ldo.dtb\",SCMEVB,SCM_LPDDR2_2GB"
+
+
+2gb interleaving evb:
+---------------------
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6dqscm/imximage_scm_lpddr2.cfg,MX6Q,DDR_MB=2048,SYS_USE_SPINOR,DEFAULT_FDT_FILE=\"imx6dqscm-2gb-evb-interleave-ldo.dtb\",INTERLEAVING_MODE,SCMEVB,SCM_LPDDR2_2GB"
+
+
+2gb interleaving evb spinor-boot:
+---------------------------------
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6dqscm/imximage_scm_lpddr2.cfg,MX6Q,DDR_MB=2048,SYS_BOOT_SPINOR,DEFAULT_FDT_FILE=\"imx6dqscm-2gb-evb-interleave-ldo.dtb\",INTERLEAVING_MODE,SCMEVB,SCM_LPDDR2_2GB"
+
+1gb interleaving evb android:
+-----------------------------
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6dqscm/imximage_scm_lpddr2.cfg,MX6Q,DDR_MB=1024,SYS_USE_SPINOR,DEFAULT_FDT_FILE=\"imx6dqscm-1gb-evb-interleave-ldo.dtb\",INTERLEAVING_MODE,SCMEVB,ANDROID_SUPPORT"
+
+
+1gb interleaving qwks_rev2:
+---------------------------
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6dqscm/imximage_scm_lpddr2.cfg,MX6Q,DDR_MB=1024,SYS_USE_SPINOR,DEFAULT_FDT_FILE=\"imx6dqscm-1gb-qwks-rev2-interleave-ldo.dtb\",INTERLEAVING_MODE"
+
+
+1gb interleaving evb spinor-boot:
+---------------------------------
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6dqscm/imximage_scm_lpddr2.cfg,MX6Q,DDR_MB=1024,SYS_BOOT_SPINOR,DEFAULT_FDT_FILE=\"imx6dqscm-1gb-evb-interleave-ldo.dtb\",INTERLEAVING_MODE,SCMEVB"
+
diff --git a/board/freescale/mx6dqscm/imximage_scm_lpddr2.cfg b/board/freescale/mx6dqscm/imximage_scm_lpddr2.cfg
new file mode 100644
index 0000000..d95b9bc
--- /dev/null
+++ b/board/freescale/mx6dqscm/imximage_scm_lpddr2.cfg
@@ -0,0 +1,600 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+#define __ASSEMBLY__
+#include <config.h>
+
+/* image version */
+
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi, sd (the board has no nand neither onenand)
+ */
+
+BOOT_FROM	sd
+
+#ifdef CONFIG_USE_PLUGIN
+/*PLUGIN    plugin-binary-file    IRAM_FREE_START_ADDR*/
+PLUGIN	board/freescale/mx6dscm/plugin.bin 0x00907000
+#else
+
+#ifdef CONFIG_SECURE_BOOT
+CSF CONFIG_CSF_SIZE
+#endif
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type           Address        Value
+ *
+ * where:
+ *	Addr-type register length (1,2 or 4 bytes)
+ *	Address	  absolute address of the register
+ *	value	  value to be stored in the register
+ */
+
+#ifdef CONFIG_SCM_LPDDR2_512MB
+/* DCD */
+/* DDR clock to 400MHz */
+DATA 4, 0x020C4018 0x00060324
+/* AHB_ROOT_CLK change divide ratio from 4 to 3 for ENET */
+DATA 4, 0x020C4014 0x00018900
+
+DATA 4 0x020C4018 0x00060324
+
+DATA 4 0x020e0798 0x00080000
+DATA 4 0x020e0758 0x00000000
+
+DATA 4 0x020E0588 0x00000030
+DATA 4 0x020E0594 0x00000030
+
+DATA 4 0x020E056c 0x00000030
+DATA 4 0x020E0578 0x00000030
+DATA 4 0x020E074c 0x00000030
+
+DATA 4 0x020E057c 0x00000030
+DATA 4 0x020E058c 0x00000000
+DATA 4 0x020E059c 0x00000030
+DATA 4 0x020E05a0 0x00000030
+DATA 4 0x020E078c 0x00000030
+
+DATA 4 0x020E0750 0x00020000
+DATA 4 0x020E05a8 0x00003030
+DATA 4 0x020E05b0 0x00003030
+DATA 4 0x020E0524 0x00003030
+DATA 4 0x020E051c 0x00003030
+DATA 4 0x020E0518 0x00003030
+DATA 4 0x020E050c 0x00003030
+DATA 4 0x020E05b8 0x00003030
+DATA 4 0x020E05c0 0x00003030
+
+DATA 4 0x020E0774 0x00020000
+
+DATA 4 0x020E0784 0x00000030
+DATA 4 0x020E0788 0x00000030
+DATA 4 0x020E0794 0x00000030
+DATA 4 0x020E079c 0x00000030
+DATA 4 0x020E07a0 0x00000030
+DATA 4 0x020E07a4 0x00000030
+DATA 4 0x020E07a8 0x00000030
+DATA 4 0x020E0748 0x00000030
+
+DATA 4 0x020E05ac 0x00000030
+DATA 4 0x020E05b4 0x00000030
+DATA 4 0x020E0528 0x00000030
+DATA 4 0x020E0520 0x00000030
+DATA 4 0x020E0514 0x00000030
+DATA 4 0x020E0510 0x00000030
+DATA 4 0x020E05bc 0x00000030
+DATA 4 0x020E05c4 0x00000030
+
+DATA 4 0x020E0590 0x00000020
+DATA 4 0x020E0598 0x00000020
+
+DATA 4 0x021b001c 0x00008000
+
+DATA 4 0x021b085c 0x1b4700c7
+
+DATA 4 0x021b0800 0xa1390003
+
+
+DATA 4 0x021b0890 0x00400000
+
+DATA 4 0x021b0848 0x44404044
+
+DATA 4 0x021b0850 0x34343A38
+
+DATA 4 0x021b083c 0x20000000
+DATA 4 0x021b0840 0x00000000
+
+DATA 4 0x021b081c 0x33333333
+DATA 4 0x021b0820 0x33333333
+DATA 4 0x021b0824 0x33333333
+DATA 4 0x021b0828 0x33333333
+
+DATA 4 0x021b082c 0xf3333333
+DATA 4 0x021b0830 0xf3333333
+DATA 4 0x021b0834 0xf3333333
+DATA 4 0x021b0838 0xf3333333
+
+DATA 4 0x021b08b8 0x00000800
+
+DATA 4 0x021b0004 0x00020036
+DATA 4 0x021b0008 0x00000000
+DATA 4 0x021b000c 0x33374133
+
+DATA 4 0x021b0010 0x00100a82
+
+DATA 4 0x021b0014 0x00000093
+
+DATA 4 0x021b0018 0x0000174C
+DATA 4 0x021b001c 0x00008050
+DATA 4 0x021b002c 0x0f9f26d2
+DATA 4 0x021b0030 0x00000010
+DATA 4 0x021b0038 0x00190778
+
+/* 1-Ch Mode */
+DATA 4 0x021b0040 0x0000004f
+
+DATA 4 0x021b0000 0x83110000
+
+/* Channel 0 */
+DATA 4 0x021b001c 0x003f8030
+DATA 4 0x021b001c 0xff0a8030
+DATA 4 0x021b001c 0x82018030
+DATA 4 0x021b001c 0x04028030
+DATA 4 0x021b001c 0x04038030
+
+DATA 4 0x021b0800 0xa1390003
+
+DATA 4 0x021b0020 0x00001800
+
+DATA 4 0x021b0818 0x00000000
+
+DATA 4 0x021b0004 0x00025576
+
+DATA 4 0x021b0404 0x00011006
+
+DATA 4 0x021b001c 0x00000000
+
+
+DATA 4 0x020c4068 0x00C03F3F
+DATA 4 0x020c406c 0x0030FC03
+DATA 4 0x020c4070 0x0FFFC000
+DATA 4 0x020c4074 0x3FF00000
+DATA 4 0x020c4078 0x00FFF300
+DATA 4 0x020c407c 0x0F0000C3
+DATA 4 0x020c4080 0x000003FF
+
+/* enable AXI cache for VDOA/VPU/IPU */
+DATA 4 0x020e0010 0xF00000CF
+/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
+DATA 4 0x020e0018 0x007F007F
+DATA 4 0x020e001c 0x007F007F
+
+#elif CONFIG_SCM_LPDDR2_2GB
+/* DDR clock to 400MHz */
+DATA 4, 0x020C4018 0x00060324
+/* AHB_ROOT_CLK change divide ratio from 4 to 3 for ENET */
+DATA 4, 0x020C4014 0x00018900
+
+DATA 4, 0x020e0798, 0x00080000
+DATA 4, 0x020e0758, 0x00000000
+
+
+
+DATA 4, 0x020E0588, 0x00000030
+DATA 4, 0x020E0594, 0x00000030
+
+DATA 4, 0x020E056c, 0x00000030
+DATA 4, 0x020E0578, 0x00000030
+DATA 4, 0x020E074c, 0x00000030
+
+DATA 4, 0x020E057c, 0x00000030
+DATA 4, 0x020E058c, 0x00000000
+DATA 4, 0x020E059c, 0x00000030
+DATA 4, 0x020E05a0, 0x00000030
+DATA 4, 0x020E078c, 0x00000030
+
+DATA 4, 0x020E0750, 0x00020000
+DATA 4, 0x020E05a8, 0x00003030
+DATA 4, 0x020E05b0, 0x00003030
+DATA 4, 0x020E0524, 0x00003030
+DATA 4, 0x020E051c, 0x00003030
+DATA 4, 0x020E0518, 0x00003030
+DATA 4, 0x020E050c, 0x00003030
+DATA 4, 0x020E05b8, 0x00003030
+DATA 4, 0x020E05c0, 0x00003030
+
+DATA 4, 0x020E0774, 0x00020000
+
+DATA 4, 0x020E0784, 0x00000030
+DATA 4, 0x020E0788, 0x00000030
+DATA 4, 0x020E0794, 0x00000030
+DATA 4, 0x020E079c, 0x00000030
+DATA 4, 0x020E07a0, 0x00000030
+DATA 4, 0x020E07a4, 0x00000030
+DATA 4, 0x020E07a8, 0x00000030
+DATA 4, 0x020E0748, 0x00000030
+
+DATA 4, 0x020E05ac, 0x00000030
+DATA 4, 0x020E05b4, 0x00000030
+DATA 4, 0x020E0528, 0x00000030
+DATA 4, 0x020E0520, 0x00000030
+DATA 4, 0x020E0514, 0x00000030
+DATA 4, 0x020E0510, 0x00000030
+DATA 4, 0x020E05bc, 0x00000030
+DATA 4, 0x020E05c4, 0x00000030
+
+
+
+DATA 4, 0x020E0590, 0x00000020
+DATA 4, 0x020E0598, 0x00000020
+
+DATA 4, 0x021b001c, 0x00008000
+DATA 4, 0x021b401c, 0x00008000
+
+DATA 4, 0x021b085c, 0x1b4700c7
+DATA 4, 0x021b485c, 0x1b4700c7
+
+DATA 4, 0x021b0800, 0xa1390003
+
+DATA 4, 0x021b0890, 0x00400000
+DATA 4, 0x021b4890, 0x00400000
+
+DATA 4, 0x021b0848, 0x44404044
+DATA 4, 0x021b4848, 0x44443A46
+
+DATA 4, 0x021b0850, 0x34343A38
+DATA 4, 0x021b4850, 0x382F3835
+
+DATA 4, 0x021b083c, 0x20000000
+DATA 4, 0x021b0840, 0x00000000
+DATA 4, 0x021b483c, 0x20000000
+DATA 4, 0x021b4840, 0x00000000
+
+DATA 4, 0x021b081c, 0x33333333
+DATA 4, 0x021b0820, 0x33333333
+DATA 4, 0x021b0824, 0x33333333
+DATA 4, 0x021b0828, 0x33333333
+DATA 4, 0x021b481c, 0x33333333
+DATA 4, 0x021b4820, 0x33333333
+DATA 4, 0x021b4824, 0x00000000
+DATA 4, 0x021b4828, 0x33333333
+DATA 4, 0x021b082c, 0xf3333333
+DATA 4, 0x021b0830, 0xf3333333
+DATA 4, 0x021b0834, 0xf3333333
+DATA 4, 0x021b0838, 0xf3333333
+DATA 4, 0x021b482c, 0xf3333333
+DATA 4, 0x021b4830, 0xf3333333
+DATA 4, 0x021b4834, 0x00000000
+DATA 4, 0x021b4838, 0xf3333333
+
+DATA 4, 0x021b08b8, 0x00000800
+DATA 4, 0x021b48b8, 0x00000800
+
+DATA 4, 0x021b0004, 0x00020036
+DATA 4, 0x021b0008, 0x00000000
+DATA 4, 0x021b000c, 0x33374133
+
+DATA 4, 0x021b0010, 0x00100a82
+
+DATA 4, 0x021b0014, 0x00000093
+
+DATA 4, 0x021b0018, 0x0000174C
+DATA 4, 0x021b001c, 0x00008050
+DATA 4, 0x021b002c, 0x0f9f26d2
+DATA 4, 0x021b0030, 0x009F0E10
+DATA 4, 0x021b0038, 0x00190778
+
+#ifdef CONFIG_INTERLEAVING_MODE
+DATA 4, 0x021b0040, 0x00000053
+#else
+DATA 4, 0x021b0040, 0x0000004f
+#endif
+
+DATA 4, 0x021b0000, 0xc3110000
+
+DATA 4, 0x021b4004, 0x00020036
+DATA 4, 0x021b4008, 0x00000000
+
+DATA 4, 0x021b400c, 0x33374133
+
+DATA 4, 0x021b4010, 0x00100a82
+
+DATA 4, 0x021b4014, 0x00000093
+
+DATA 4, 0x021b4018, 0x0000174C
+DATA 4, 0x021b401c, 0x00008050
+
+DATA 4, 0x021b402c, 0x0f9f26d2
+
+DATA 4, 0x021b4030, 0x009F0E10
+
+DATA 4, 0x021b4038, 0x00190778
+
+#ifdef CONFIG_INTERLEAVING_MODE
+DATA 4, 0x021b4040, 0x00000013
+#else
+DATA 4, 0x021b4040, 0x00000017
+#endif
+
+DATA 4, 0x021b4000, 0xc3110000
+
+/* Channel 0 */
+/* CS0 */
+DATA 4, 0x021b001c, 0x003f8030
+DATA 4, 0x021b001c, 0xff0a8030
+DATA 4, 0x021b001c, 0x82018030
+DATA 4, 0x021b001c, 0x04028030
+DATA 4, 0x021b001c, 0x04038030
+DATA 4, 0x021b001c, 0x01038030
+/* CS1 */
+DATA 4, 0x021b001c, 0x003f8038
+DATA 4, 0x021b001c, 0xff0a8038
+DATA 4, 0x021b001c, 0x82018038
+DATA 4, 0x021b001c, 0x04028038
+DATA 4, 0x021b001c, 0x04038038
+DATA 4, 0x021b001c, 0x01038038
+
+/* Channel 1 */
+/* CS0 */
+DATA 4, 0x021b401c, 0x003f8030
+DATA 4, 0x021b401c, 0xff0a8030
+DATA 4, 0x021b401c, 0x82018030
+DATA 4, 0x021b401c, 0x04028030
+DATA 4, 0x021b401c, 0x04038030
+DATA 4, 0x021b401c, 0x01038030
+/* CS1 */
+DATA 4, 0x021b401c, 0x003f8038
+DATA 4, 0x021b401c, 0xff0a8038
+DATA 4, 0x021b401c, 0x82018038
+DATA 4, 0x021b401c, 0x04028038
+DATA 4, 0x021b401c, 0x04038038
+DATA 4, 0x021b401c, 0x01038038
+DATA 4, 0x021b4800, 0xa1390003
+
+DATA 4, 0x021b0020, 0x00001800
+DATA 4, 0x021b4020, 0x00001800
+
+DATA 4, 0x021b0818, 0x00000000
+DATA 4, 0x021b4818, 0x00000000
+
+DATA 4, 0x021b0004, 0x00025576
+DATA 4, 0x021b4004, 0x00025576
+
+DATA 4, 0x021b0404, 0x00011006
+DATA 4, 0x021b4404, 0x00011006
+
+DATA 4, 0x021b001c, 0x00000000
+DATA 4, 0x021b401c, 0x00000000
+
+/* enable clocks */
+DATA 4, 0x020c4068, 0x00C03F3F
+DATA 4, 0x020c406c, 0x0030FC03
+DATA 4, 0x020c4070, 0x0FFFC000
+DATA 4, 0x020c4074, 0x3FF00000
+DATA 4, 0x020c4078, 0x00FFF300
+DATA 4, 0x020c407c, 0x0F0000C3
+DATA 4, 0x020c4080, 0x000003FF
+
+/* enable AXI cache for VDOA/VPU/IPU */
+DATA 4, 0x020e0010, 0xF00000CF
+/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
+DATA 4, 0x020e0018, 0x007F007F
+DATA 4, 0x020e001c, 0x007F007F
+
+#else
+/* DCD */
+/* DDR clock to 400MHz */
+DATA 4, 0x020C4018 0x00060324
+/* AHB_ROOT_CLK change divide ratio from 4 to 3 for ENET */
+DATA 4, 0x020C4014 0x00018900
+
+/* DSE to 80 ohms, 100K PD on DQS */
+DATA 4 0x020e0798 0x00080000
+DATA 4 0x020e0758 0x00000000
+
+
+
+DATA 4, 0x020E0588, 0x00000030
+DATA 4, 0x020E0594, 0x00000030
+
+DATA 4, 0x020E056c, 0x00000030
+DATA 4, 0x020E0578, 0x00000030
+DATA 4, 0x020E074c, 0x00000030
+
+DATA 4, 0x020E057c, 0x00000030
+DATA 4, 0x020E058c, 0x00000000
+DATA 4, 0x020E059c, 0x00000030
+DATA 4, 0x020E05a0, 0x00000030
+DATA 4, 0x020E078c, 0x00000030
+
+DATA 4, 0x020E0750, 0x00020000
+DATA 4, 0x020E05a8, 0x00003030
+DATA 4, 0x020E05b0, 0x00003030
+DATA 4, 0x020E0524, 0x00003030
+DATA 4, 0x020E051c, 0x00003030
+DATA 4, 0x020E0518, 0x00003030
+DATA 4, 0x020E050c, 0x00003030
+DATA 4, 0x020E05b8, 0x00003030
+DATA 4, 0x020E05c0, 0x00003030
+
+DATA 4, 0x020E0774, 0x00020000
+
+DATA 4, 0x020E0784, 0x00000030
+DATA 4, 0x020E0788, 0x00000030
+DATA 4, 0x020E0794, 0x00000030
+DATA 4, 0x020E079c, 0x00000030
+DATA 4, 0x020E07a0, 0x00000030
+DATA 4, 0x020E07a4, 0x00000030
+DATA 4, 0x020E07a8, 0x00000030
+DATA 4, 0x020E0748, 0x00000030
+
+DATA 4, 0x020E05ac, 0x00000030
+DATA 4, 0x020E05b4, 0x00000030
+DATA 4, 0x020E0528, 0x00000030
+DATA 4, 0x020E0520, 0x00000030
+DATA 4, 0x020E0514, 0x00000030
+DATA 4, 0x020E0510, 0x00000030
+DATA 4, 0x020E05bc, 0x00000030
+DATA 4, 0x020E05c4, 0x00000030
+
+
+
+DATA 4, 0x020E0590, 0x00000020
+DATA 4, 0x020E0598, 0x00000020
+
+
+/* DDR setup */
+DATA 4, 0x021b001c, 0x00008000
+DATA 4, 0x021b401c, 0x00008000
+
+/*SCM CONF*/
+
+DATA 4, 0x021b085c, 0x1b4700c7
+DATA 4, 0x021b485c, 0x1b4700c7
+
+DATA 4, 0x021b0800, 0xa1390003
+
+/* calibration required */
+DATA 4, 0x021b0890, 0x00400000
+DATA 4, 0x021b4890, 0x00400000
+
+/* calibration required */
+/*SCM CONF*/
+
+DATA 4, 0x021b0848, 0x44404044
+DATA 4, 0x021b4848, 0x44443A46
+
+DATA 4, 0x021b0850, 0x34343A38
+DATA 4, 0x021b4850, 0x3E2E483C
+
+DATA 4, 0x021b083c, 0x20000000
+DATA 4, 0x021b0840, 0x00000000
+DATA 4, 0x021b483c, 0x20000000
+DATA 4, 0x021b4840, 0x00000000
+
+DATA 4, 0x021b081c, 0x33333333
+DATA 4, 0x021b0820, 0x33333333
+DATA 4, 0x021b0824, 0x33333333
+DATA 4, 0x021b0828, 0x33333333
+DATA 4, 0x021b481c, 0x33333333
+DATA 4, 0x021b4820, 0x33333333
+DATA 4, 0x021b4824, 0x33333333
+DATA 4, 0x021b4828, 0x33333333
+DATA 4, 0x021b082c, 0xf3333333
+DATA 4, 0x021b0830, 0xf3333333
+DATA 4, 0x021b0834, 0xf3333333
+DATA 4, 0x021b0838, 0xf3333333
+DATA 4, 0x021b482c, 0xf3333333
+DATA 4, 0x021b4830, 0xf3333333
+DATA 4, 0x021b4834, 0xf3333333
+DATA 4, 0x021b4838, 0xf3333333
+
+DATA 4, 0x021b08b8, 0x00000800
+DATA 4, 0x021b48b8, 0x00000800
+
+DATA 4, 0x021b0004, 0x00020036
+DATA 4, 0x021b0008, 0x00000000
+DATA 4, 0x021b000c, 0x33374133
+
+DATA 4, 0x021b0010, 0x00100a82
+
+DATA 4, 0x021b0014, 0x00000093
+
+DATA 4, 0x021b0018, 0x0000174C
+DATA 4, 0x021b001c, 0x00008050
+DATA 4, 0x021b002c, 0x0f9f26d2
+DATA 4, 0x021b0030, 0x00000010
+DATA 4, 0x021b0038, 0x00190778
+#ifdef CONFIG_INTERLEAVING_MODE
+DATA 4, 0x021b0040, 0x00000053
+#else
+DATA 4, 0x021b0040, 0x0000004f
+#endif
+
+DATA 4, 0x021b0000, 0x83110000
+
+DATA 4, 0x021b4008, 0x00000000
+
+DATA 4, 0x021b400c, 0x33374133
+DATA 4, 0x021b4004, 0x00020036
+DATA 4, 0x021b4010, 0x00100a82
+
+DATA 4, 0x021b4014, 0x00000093
+
+DATA 4, 0x021b4018, 0x0000174C
+DATA 4, 0x021b401c, 0x00008050
+
+DATA 4, 0x021b402c, 0x0f9f26d2
+
+DATA 4, 0x021b4030, 0x00000010
+
+DATA 4, 0x021b4038, 0x00190778
+#ifdef CONFIG_INTERLEAVING_MODE
+DATA 4, 0x021b4040, 0x00000013
+#else
+DATA 4, 0x021b4040, 0x00000017
+#endif
+
+DATA 4, 0x021b4000, 0x83110000
+
+/* Channel 0 */
+DATA 4, 0x021b001c, 0x003f8030
+DATA 4, 0x021b001c, 0xff0a8030
+DATA 4, 0x021b001c, 0x82018030
+DATA 4, 0x021b001c, 0x04028030
+DATA 4, 0x021b001c, 0x04038030
+
+/* Channel 1 */
+DATA 4, 0x021b401c, 0x003f8030
+DATA 4, 0x021b401c, 0xff0a8030
+DATA 4, 0x021b401c, 0x82018030
+DATA 4, 0x021b401c, 0x04028030
+DATA 4, 0x021b401c, 0x04038030
+
+DATA 4, 0x021b0800, 0xa1390003
+
+DATA 4, 0x021b0020, 0x00001800
+DATA 4, 0x021b4020, 0x00001800
+
+DATA 4, 0x021b0818, 0x00000000
+DATA 4, 0x021b4818, 0x00000000
+
+DATA 4, 0x021b0004, 0x00025576
+DATA 4, 0x021b4004, 0x00025576
+
+DATA 4, 0x021b0404, 0x00011006
+DATA 4, 0x021b4404, 0x00011006
+
+DATA 4, 0x021b001c, 0x00000000
+DATA 4, 0x021b401c, 0x00000000
+
+/* enable clocks */
+DATA 4, 0x020c4068, 0x00C03F3F
+DATA 4, 0x020c406c, 0x0030FC03
+DATA 4, 0x020c4070, 0x0FFFC000
+DATA 4, 0x020c4074, 0x3FF00000
+DATA 4, 0x020c4078, 0x00FFF300
+DATA 4, 0x020c407c, 0x0F0000C3
+DATA 4, 0x020c4080, 0x000003FF
+
+/* enable AXI cache for VDOA/VPU/IPU */
+DATA 4, 0x020e0010, 0xF00000CF
+/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
+DATA 4, 0x020e0018, 0x007F007F
+DATA 4, 0x020e001c, 0x007F007F
+#endif /*CONFIG_SCM_LPDDR2_2GB*/
+#endif
diff --git a/board/freescale/mx6dqscm/mx6dqscm.c b/board/freescale/mx6dqscm/mx6dqscm.c
new file mode 100644
index 0000000..de08e95
--- /dev/null
+++ b/board/freescale/mx6dqscm/mx6dqscm.c
@@ -0,0 +1,1040 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/errno.h>
+#include <asm/gpio.h>
+#include <asm/imx-common/mxc_i2c.h>
+#include <asm/imx-common/iomux-v3.h>
+#include <asm/imx-common/boot_mode.h>
+#include <asm/imx-common/video.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <asm/arch/mxc_hdmi.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/io.h>
+#include <asm/arch/sys_proto.h>
+#include <i2c.h>
+#include <power/pmic.h>
+#include <power/pfuze100_pmic.h>
+#include "../common/pfuze.h"
+#include <asm/arch/mx6-ddr.h>
+#include <usb.h>
+#include <micrel.h>
+#ifdef CONFIG_CMD_SATA
+#include <asm/imx-common/sata.h>
+#endif
+#ifdef CONFIG_FSL_FASTBOOT
+#include <fsl_fastboot.h>
+#ifdef CONFIG_ANDROID_RECOVERY
+#include <recovery.h>
+#endif
+#endif /*CONFIG_FSL_FASTBOOT*/
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
+	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |			\
+	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |			\
+	PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |			\
+	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
+	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+
+#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
+	PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
+
+#define I2C_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
+	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |	\
+	PAD_CTL_ODE | PAD_CTL_SRE_FAST)
+
+#define OTG_ID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |		\
+	PAD_CTL_PUS_47K_UP  | PAD_CTL_SPEED_LOW |		\
+	PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define I2C_PMIC	1
+
+#define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL)
+
+#ifdef CONFIG_SCMEVB
+#define DISP0_PWR_EN	IMX_GPIO_NR(1, 21)
+#else
+#define DISP0_PWR_EN	IMX_GPIO_NR(1, 18)
+#endif
+
+int dram_init(void)
+{
+#ifdef CONFIG_INTERLEAVING_MODE
+	u32 mdmisc = readl(MMDC_P0_BASE_ADDR + 0x18);
+
+	gd->ram_size = imx_ddr_size() << ((mdmisc & 0x00000004) ? 1 : 0);
+#else
+	gd->ram_size = imx_ddr_size();
+#endif
+
+	return 0;
+}
+
+#if !defined(CONFIG_INTERLEAVING_MODE) && !defined(CONFIG_SCM_LPDDR2_512MB)
+void dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_0;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_0_SIZE;
+	gd->bd->bi_dram[1].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[1].size = PHYS_SDRAM_1_SIZE;
+}
+#endif
+#ifdef CONFIG_SCMHVB
+iomux_v3_cfg_t const uart_pads[] = {
+	MX6_PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+#else
+static iomux_v3_cfg_t const uart_pads[] = {
+	MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+#endif
+
+static iomux_v3_cfg_t const enet_pads[] = {
+	MX6_PAD_ENET_MDIO__ENET_MDIO		| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET_MDC__ENET_MDC		| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_TXC__RGMII_TXC	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_TD0__RGMII_TD0	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_TD1__RGMII_TD1	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_TD2__RGMII_TD2	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_TD3__RGMII_TD3	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+#ifdef CONFIG_QWKS_REV3
+	MX6_PAD_GPIO_16__ENET_REF_CLK	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+#else
+	MX6_PAD_ENET_REF_CLK__ENET_TX_CLK	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+#endif
+	MX6_PAD_RGMII_RXC__RGMII_RXC	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_RD0__RGMII_RD0	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_RD1__RGMII_RD1	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_RD2__RGMII_RD2	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_RD3__RGMII_RD3	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	/* AR8031 PHY Reset */
+	MX6_PAD_ENET_CRS_DV__GPIO1_IO25		| MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static void setup_iomux_enet(void)
+{
+	imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
+
+	/* Reset AR8031 PHY */
+	gpio_direction_output(IMX_GPIO_NR(1, 25) , 0);
+	mdelay(10);
+	gpio_set_value(IMX_GPIO_NR(1, 25), 1);
+	udelay(100);
+}
+
+static iomux_v3_cfg_t const usdhc2_pads[] = {
+	MX6_PAD_SD2_CLK__SD2_CLK	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD2_CMD__SD2_CMD	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD2_DAT0__SD2_DATA0	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD2_DAT1__SD2_DATA1	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD2_DAT2__SD2_DATA2	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD2_DAT3__SD2_DATA3	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_NANDF_D4__SD2_DATA4	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_NANDF_D5__SD2_DATA5	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_NANDF_D6__SD2_DATA6	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_NANDF_D7__SD2_DATA7	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
+#ifdef CONFIG_SCMEVB
+	MX6_PAD_NANDF_D2__GPIO2_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
+#else
+	MX6_PAD_GPIO_4__GPIO1_IO04	| MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
+#endif
+};
+
+static iomux_v3_cfg_t const usdhc3_pads[] = {
+	MX6_PAD_SD3_CLK__SD3_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_CMD__SD3_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+#ifndef CONFIG_QWKS_REV3
+	MX6_PAD_SD3_DAT4__GPIO7_IO01 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+#endif
+	MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_NANDF_D0__GPIO2_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
+};
+
+static iomux_v3_cfg_t const usdhc4_pads[] = {
+	MX6_PAD_SD4_CLK__SD4_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_CMD__SD4_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+};
+
+#ifdef CONFIG_MXC_SPI
+static iomux_v3_cfg_t const ecspi1_pads[] = {
+	MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
+	MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
+	MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
+	MX6_PAD_EIM_EB2__GPIO2_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static void setup_spi(void)
+{
+	imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
+}
+
+int board_spi_cs_gpio(unsigned bus, unsigned cs)
+{
+	return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(2, 30)) : -1;
+}
+#endif
+
+static iomux_v3_cfg_t const rgb_pads[] = {
+	MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_DI0_PIN4__IPU1_DI0_PIN04 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_SD1_DAT3__GPIO1_IO21 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static void enable_rgb(struct display_info_t const *dev)
+{
+	imx_iomux_v3_setup_multiple_pads(rgb_pads, ARRAY_SIZE(rgb_pads));
+	gpio_direction_output(DISP0_PWR_EN, 1);
+}
+
+static struct i2c_pads_info i2c_pad_info1 = {
+	.scl = {
+		.i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | I2C_PAD,
+		.gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | I2C_PAD,
+		.gp = IMX_GPIO_NR(4, 12)
+	},
+	.sda = {
+		.i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD,
+		.gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD,
+		.gp = IMX_GPIO_NR(4, 13)
+	}
+};
+
+iomux_v3_cfg_t const pcie_pads[] = {
+	MX6_PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL), /* POWER */
+	MX6_PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL), /* RESET */
+};
+
+static void setup_pcie(void)
+{
+	imx_iomux_v3_setup_multiple_pads(pcie_pads, ARRAY_SIZE(pcie_pads));
+}
+
+iomux_v3_cfg_t const di0_pads[] = {
+	MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK,	/* DISP0_CLK */
+	MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02,		/* DISP0_HSYNC */
+	MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03,		/* DISP0_VSYNC */
+};
+
+iomux_v3_cfg_t const lvds_pwr_en_pads[] = {
+	MX6_PAD_SD1_CMD__GPIO1_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static void setup_iomux_uart(void)
+{
+	imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
+}
+
+#ifdef CONFIG_FSL_ESDHC
+struct fsl_esdhc_cfg usdhc_cfg[3] = {
+	{USDHC2_BASE_ADDR},
+	{USDHC3_BASE_ADDR},
+	{USDHC4_BASE_ADDR},
+};
+
+#ifdef CONFIG_SCMEVB
+	#define USDHC2_CD_GPIO IMX_GPIO_NR(2, 2)
+#else
+	#define USDHC2_CD_GPIO  IMX_GPIO_NR(1, 4)
+#endif
+
+#ifdef CONFIG_QWKS_REV3
+#define USDHC3_CD_GPIO  IMX_GPIO_NR(7, 1)
+#else
+#define USDHC3_CD_GPIO	IMX_GPIO_NR(2, 0)
+#endif
+
+int board_mmc_get_env_dev(int devno)
+{
+	return devno - 1;
+}
+
+int mmc_map_to_kernel_blk(int devno)
+{
+	return devno + 1;
+}
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+	int ret = 0;
+
+	switch (cfg->esdhc_base) {
+	case USDHC2_BASE_ADDR:
+		ret = !gpio_get_value(USDHC2_CD_GPIO);
+		break;
+	case USDHC3_BASE_ADDR:
+#ifdef CONFIG_SCMHVB
+		ret = 1;
+#else
+		ret = !gpio_get_value(USDHC3_CD_GPIO);
+#endif
+		break;
+	case USDHC4_BASE_ADDR:
+		ret = 1; /* eMMC/uSDHC4 is always present */
+		break;
+	}
+
+	return ret;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+	int ret;
+	int i;
+
+	/*
+	 * According to the board_mmc_init() the following map is done:
+	 * (U-Boot device node)    (Physical Port)
+	 * mmc0                    SD2
+	 * mmc1                    SD3
+	 * mmc2                    eMMC
+	 */
+	for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
+		switch (i) {
+		case 0:
+			imx_iomux_v3_setup_multiple_pads(
+				usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
+			gpio_direction_input(USDHC2_CD_GPIO);
+			usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+			break;
+		case 1:
+#ifndef CONFIG_SCMHVB
+			imx_iomux_v3_setup_multiple_pads(
+				usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
+			gpio_direction_input(USDHC3_CD_GPIO);
+#endif
+			usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+			break;
+		case 2:
+			imx_iomux_v3_setup_multiple_pads(
+				usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
+			usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
+			break;
+		default:
+			printf("Warning: you configured more ");
+			printf("USDHC controllers ");
+			printf("(%d) than supported by the board (%d)\n",
+			       i + 1, CONFIG_SYS_FSL_USDHC_NUM);
+			return -EINVAL;
+		}
+
+		ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
+		if (ret)
+			return ret;
+	}
+
+	return 0;
+}
+#endif
+
+int mx6_rgmii_rework(struct phy_device *phydev)
+{
+	/* add necessary delays for RGMII,
+	 * there are no board skew delays added
+	 * additional rx data delay = 0, rx clk delay = 0.3ns, total = 1.5ns
+	 * additional tx data delay = -0.42ns, tx clk delay = 0.96ns,
+	 * total = 1.38ns
+	 */
+
+	if (ksz9031_phy_extended_write(phydev, 0x2,
+				       MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW,
+				       MII_KSZ9031_MOD_DATA_NO_POST_INC,
+				       0x0070))
+		return -EIO;
+
+	if (ksz9031_phy_extended_write(phydev, 0x2,
+				       MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW,
+				       MII_KSZ9031_MOD_DATA_NO_POST_INC,
+				       0x7777))
+		return -EIO;
+
+	if (ksz9031_phy_extended_write(phydev, 0x2,
+				       MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW,
+				       MII_KSZ9031_MOD_DATA_NO_POST_INC,
+				       0x0000))
+		return -EIO;
+
+	if (ksz9031_phy_extended_write(phydev, 0x2,
+				       MII_KSZ9031_EXT_RGMII_CLOCK_SKEW,
+				       MII_KSZ9031_MOD_DATA_NO_POST_INC,
+				       0x03f4))
+		return -EIO;
+
+	return 0;
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+	mx6_rgmii_rework(phydev);
+
+	if (phydev->drv->config)
+		phydev->drv->config(phydev);
+
+	return 0;
+}
+
+#if defined(CONFIG_VIDEO_IPUV3)
+static void disable_lvds(struct display_info_t const *dev)
+{
+	struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
+
+	int reg = readl(&iomux->gpr[2]);
+
+	reg &= ~(IOMUXC_GPR2_LVDS_CH0_MODE_MASK |
+		 IOMUXC_GPR2_LVDS_CH1_MODE_MASK);
+
+	writel(reg, &iomux->gpr[2]);
+#ifndef CONFIG_SCMEVB
+	gpio_direction_output(DISP0_PWR_EN, 0);
+#endif
+}
+
+static void do_enable_hdmi(struct display_info_t const *dev)
+{
+	disable_lvds(dev);
+	imx_enable_hdmi_phy();
+}
+
+static void enable_lvds(struct display_info_t const *dev)
+{
+	struct iomuxc *iomux = (struct iomuxc *)
+				IOMUXC_BASE_ADDR;
+	u32 reg = readl(&iomux->gpr[2]);
+
+	reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT |
+	       IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT;
+	writel(reg, &iomux->gpr[2]);
+#ifndef CONFIG_SCMEVB
+	gpio_direction_output(DISP0_PWR_EN, 1);
+#endif
+}
+
+struct display_info_t const displays[] = {{
+	.bus	= -1,
+	.addr	= 0,
+	.pixfmt	= IPU_PIX_FMT_RGB666,
+	.detect	= NULL,
+	.enable	= enable_lvds,
+	.mode	= {
+		.name           = "Hannstar-XGA",
+		.refresh        = 60,
+		.xres           = 1024,
+		.yres           = 768,
+		.pixclock       = 15385,
+		.left_margin    = 220,
+		.right_margin   = 40,
+		.upper_margin   = 21,
+		.lower_margin   = 7,
+		.hsync_len      = 60,
+		.vsync_len      = 10,
+		.sync           = FB_SYNC_EXT,
+		.vmode          = FB_VMODE_NONINTERLACED
+} }, {
+	.bus	= -1,
+	.addr	= 0,
+	.pixfmt	= IPU_PIX_FMT_RGB24,
+	.detect	= NULL,
+	.enable	= do_enable_hdmi,
+	.mode	= {
+		.name           = "HDMI",
+		.refresh        = 60,
+		.xres           = 640,
+		.yres           = 480,
+		.pixclock       = 39721,
+		.left_margin    = 48,
+		.right_margin   = 16,
+		.upper_margin   = 33,
+		.lower_margin   = 10,
+		.hsync_len      = 96,
+		.vsync_len      = 2,
+		.sync           = 0,
+		.vmode          = FB_VMODE_NONINTERLACED
+} }, {
+	.bus	= 0,
+	.addr	= 0,
+	.pixfmt	= IPU_PIX_FMT_RGB24,
+	.detect	= NULL,
+	.enable	= enable_rgb,
+	.mode	= {
+		.name           = "SEIKO-WVGA",
+		.refresh        = 60,
+		.xres           = 800,
+		.yres           = 480,
+		.pixclock       = 29850,
+		.left_margin    = 89,
+		.right_margin   = 164,
+		.upper_margin   = 23,
+		.lower_margin   = 10,
+		.hsync_len      = 10,
+		.vsync_len      = 10,
+		.sync           = 0,
+		.vmode          = FB_VMODE_NONINTERLACED
+} } };
+size_t display_count = ARRAY_SIZE(displays);
+
+static void setup_display(void)
+{
+	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+	struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
+	int reg;
+
+	/* Setup HSYNC, VSYNC, DISP_CLK for debugging purposes */
+	imx_iomux_v3_setup_multiple_pads(di0_pads, ARRAY_SIZE(di0_pads));
+
+	enable_ipu_clock();
+	imx_setup_hdmi();
+
+	/* Turn on LDB0, LDB1, IPU,IPU DI0 clocks */
+	reg = readl(&mxc_ccm->CCGR3);
+	reg |=  MXC_CCM_CCGR3_LDB_DI0_MASK | MXC_CCM_CCGR3_LDB_DI1_MASK;
+	writel(reg, &mxc_ccm->CCGR3);
+
+	/* set LDB0, LDB1 clk select to 011/011 */
+	reg = readl(&mxc_ccm->cs2cdr);
+	reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
+		 | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
+	reg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
+	      | (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
+	writel(reg, &mxc_ccm->cs2cdr);
+
+	reg = readl(&mxc_ccm->cscmr2);
+	reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV | MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV;
+	writel(reg, &mxc_ccm->cscmr2);
+
+	reg = readl(&mxc_ccm->chsccdr);
+	reg |= (CHSCCDR_CLK_SEL_LDB_DI0
+		<< MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
+	reg |= (CHSCCDR_CLK_SEL_LDB_DI0
+		<< MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET);
+	writel(reg, &mxc_ccm->chsccdr);
+
+	reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
+	     | IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW
+	     | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
+	     | IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
+	     | IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
+	     | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
+	     | IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
+	     | IOMUXC_GPR2_LVDS_CH0_MODE_DISABLED
+	     | IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0;
+	writel(reg, &iomux->gpr[2]);
+
+	reg = readl(&iomux->gpr[3]);
+	reg = (reg & ~(IOMUXC_GPR3_LVDS1_MUX_CTL_MASK
+	     | IOMUXC_GPR3_HDMI_MUX_CTL_MASK))
+	     | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
+	     << IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET);
+	writel(reg, &iomux->gpr[3]);
+#ifndef CONFIG_SCMEVB
+	imx_iomux_v3_setup_multiple_pads(lvds_pwr_en_pads,
+					 ARRAY_SIZE(lvds_pwr_en_pads));
+#endif
+}
+#endif /* CONFIG_VIDEO_IPUV3 */
+
+/*
+ * Do not overwrite the console
+ * Use always serial for U-Boot console
+ */
+int overwrite_console(void)
+{
+	return 1;
+}
+
+static void setup_fec(void)
+{
+	return;
+}
+
+int board_eth_init(bd_t *bis)
+{
+	setup_iomux_enet();
+	setup_pcie();
+
+	return cpu_eth_init(bis);
+}
+
+#ifdef CONFIG_USB_EHCI_MX6
+#define USB_OTHERREGS_OFFSET	0x800
+#define UCTRL_PWR_POL		(1 << 9)
+
+static iomux_v3_cfg_t const usb_otg_pads[] = {
+#ifdef CONFIG_QWKS_REV3
+	MX6_PAD_KEY_ROW4__USB_OTG_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_KEY_COL4__USB_OTG_OC | MUX_PAD_CTRL(NO_PAD_CTRL),
+#else
+	MX6_PAD_EIM_D22__USB_OTG_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
+#endif
+#ifdef CONFIG_SCMEVB
+	MX6_PAD_ENET_RX_ER__USB_OTG_ID | MUX_PAD_CTRL(OTG_ID_PAD_CTRL),
+#else
+	MX6_PAD_GPIO_1__USB_OTG_ID | MUX_PAD_CTRL(OTG_ID_PAD_CTRL),
+#endif
+};
+
+static iomux_v3_cfg_t const usb_hc1_pads[] = {
+	MX6_PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static void setup_usb(void)
+{
+	imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
+					 ARRAY_SIZE(usb_otg_pads));
+
+	/*
+	 * set daisy chain for otg_pin_id on 6q.
+	 * for 6dl, this bit is reserved
+	 */
+#ifdef CONFIG_SCMEVB
+	imx_iomux_set_gpr_register(1, 13, 1, 0);
+#else
+	imx_iomux_set_gpr_register(1, 13, 1, 1);
+#endif
+
+	imx_iomux_v3_setup_multiple_pads(usb_hc1_pads,
+					 ARRAY_SIZE(usb_hc1_pads));
+}
+
+int board_ehci_hcd_init(int port)
+{
+	u32 *usbnc_usb_ctrl;
+
+	if (port > 1)
+		return -EINVAL;
+
+	usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
+				 port * 4);
+
+	setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
+
+	return 0;
+}
+
+int board_ehci_power(int port, int on)
+{
+	switch (port) {
+	case 0:
+		break;
+	case 1:
+		if (on)
+			gpio_direction_output(IMX_GPIO_NR(1, 29), 1);
+		else
+			gpio_direction_output(IMX_GPIO_NR(1, 29), 0);
+		break;
+	default:
+		printf("MXC USB port %d not yet supported\n", port);
+		return -EINVAL;
+	}
+
+	return 0;
+}
+#endif
+
+int board_early_init_f(void)
+{
+	setup_iomux_uart();
+#if defined(CONFIG_VIDEO_IPUV3)
+	setup_display();
+#endif
+
+	return 0;
+}
+
+int board_init(void)
+{
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+#ifdef CONFIG_MXC_SPI
+	setup_spi();
+#endif
+	setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
+
+#ifdef CONFIG_USB_EHCI_MX6
+	setup_usb();
+#endif
+
+#ifdef CONFIG_CMD_SATA
+	setup_sata();
+#endif
+
+#ifdef CONFIG_FEC_MXC
+	setup_fec();
+#endif
+	return 0;
+}
+
+int power_init_board(void)
+{
+	struct pmic *pfuze;
+	unsigned int reg;
+	int ret;
+
+	pfuze = pfuze_common_init(I2C_PMIC);
+	if (!pfuze)
+		return -ENODEV;
+
+	ret = pfuze_mode_init(pfuze, APS_PFM);
+	if (ret < 0)
+		return ret;
+
+	/* set SW3A to 1.25V for LPDDR2 */
+	pmic_reg_read(pfuze, PFUZE100_SW3AVOL, &reg);
+	reg &= ~0x3f;
+	reg |= 0x22;
+	pmic_reg_write(pfuze, PFUZE100_SW3AVOL, reg);
+
+	/* set SW2 to 3.2V */
+	pmic_reg_read(pfuze, PFUZE100_SW2VOL, &reg);
+	reg &= ~0x7f;
+	reg |= 0x72;
+	pmic_reg_write(pfuze, PFUZE100_SW2VOL, reg);
+
+	/* set VGEN1 to 1.5V */
+	pmic_reg_read(pfuze, PFUZE100_VGEN1VOL, &reg);
+	reg &= ~0x0f;
+	reg |= 0x0e;
+	pmic_reg_write(pfuze, PFUZE100_VGEN1VOL, reg);
+
+	/* set VGEN3 to 2.8V */
+	pmic_reg_read(pfuze, PFUZE100_VGEN3VOL, &reg);
+	reg &= ~0x0f;
+	reg |= 0x0a;
+	pmic_reg_write(pfuze, PFUZE100_VGEN3VOL, reg);
+
+	/* set VGEN4 to 2.5V */
+	pmic_reg_read(pfuze, PFUZE100_VGEN4VOL, &reg);
+	reg &= ~0x0f;
+	reg |= 0x07;
+	pmic_reg_write(pfuze, PFUZE100_VGEN4VOL, reg);
+
+	/* set VGEN5 to 3.3V */
+	pmic_reg_read(pfuze, PFUZE100_VGEN5VOL, &reg);
+	reg &= ~0x0f;
+#ifdef CONFIG_QWKS_REV3
+	reg |= 0x07;
+#else
+	reg |= 0x0f;
+#endif
+	pmic_reg_write(pfuze, PFUZE100_VGEN5VOL, reg);
+
+	/* set VGEN6 to 3.2V */
+	pmic_reg_read(pfuze, PFUZE100_VGEN6VOL, &reg);
+	reg &= ~0x0f;
+	reg |= 0x0e;
+	pmic_reg_write(pfuze, PFUZE100_VGEN6VOL, reg);
+
+	/* set SW1AB staby volatage 0.975V*/
+	pmic_reg_read(pfuze, PFUZE100_SW1ABSTBY, &reg);
+	reg &= ~0x3f;
+	reg |= 0x1b;
+	pmic_reg_write(pfuze, PFUZE100_SW1ABSTBY, reg);
+
+	/* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
+	pmic_reg_read(pfuze, PFUZE100_SW1ABCONF, &reg);
+	reg &= ~0xc0;
+	reg |= 0x40;
+	pmic_reg_write(pfuze, PFUZE100_SW1ABCONF, reg);
+
+	/* set SW1C staby volatage 0.975V*/
+	pmic_reg_read(pfuze, PFUZE100_SW1CSTBY, &reg);
+	reg &= ~0x3f;
+	reg |= 0x1b;
+	pmic_reg_write(pfuze, PFUZE100_SW1CSTBY, reg);
+
+	/* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */
+	pmic_reg_read(pfuze, PFUZE100_SW1CCONF, &reg);
+	reg &= ~0xc0;
+	reg |= 0x40;
+	pmic_reg_write(pfuze, PFUZE100_SW1CCONF, reg);
+
+	return 0;
+}
+
+#ifdef CONFIG_LDO_BYPASS_CHECK
+void ldo_mode_set(int ldo_bypass)
+{
+	unsigned int value;
+	int is_400M;
+	unsigned char vddarm;
+	struct pmic *p = pmic_get("PFUZE100");
+
+	if (!p) {
+		printf("No PMIC found!\n");
+		return;
+	}
+
+	/* increase VDDARM/VDDSOC to support 1.2G chip */
+	if (check_1_2G()) {
+		ldo_bypass = 0;	/* ldo_enable on 1.2G chip */
+		printf("1.2G chip, increase VDDARM_IN/VDDSOC_IN\n");
+		/* increase VDDARM to 1.425V */
+		pmic_reg_read(p, PFUZE100_SW1ABVOL, &value);
+		value &= ~0x3f;
+		value |= 0x2d;
+		pmic_reg_write(p, PFUZE100_SW1ABVOL, value);
+
+		/* increase VDDSOC to 1.425V */
+		pmic_reg_read(p, PFUZE100_SW1CVOL, &value);
+		value &= ~0x3f;
+		value |= 0x2d;
+		pmic_reg_write(p, PFUZE100_SW1CVOL, value);
+	}
+	/* switch to ldo_bypass mode , boot on 800Mhz */
+	if (ldo_bypass) {
+		prep_anatop_bypass();
+
+		/* decrease VDDARM for 400Mhz DQ:1.1V */
+		pmic_reg_read(p, PFUZE100_SW1ABVOL, &value);
+		value &= ~0x3f;
+		value |= 0x20;
+
+		pmic_reg_write(p, PFUZE100_SW1ABVOL, value);
+
+		/* increase VDDSOC to 1.3V */
+		pmic_reg_read(p, PFUZE100_SW1CVOL, &value);
+		value &= ~0x3f;
+		value |= 0x28;
+		pmic_reg_write(p, PFUZE100_SW1CVOL, value);
+
+		/*
+		 * MX6Q:
+		 * VDDARM:1.15V@800M; VDDSOC:1.175V@800M
+		 * VDDARM:0.975V@400M; VDDSOC:1.175V@400M
+		 */
+		is_400M = set_anatop_bypass(2);
+
+		if (is_400M)
+			vddarm = 0x1b;
+		else
+			vddarm = 0x22;
+
+		pmic_reg_read(p, PFUZE100_SW1ABVOL, &value);
+		value &= ~0x3f;
+		value |= vddarm;
+		pmic_reg_write(p, PFUZE100_SW1ABVOL, value);
+
+		/* decrease VDDSOC to 1.175V */
+		pmic_reg_read(p, PFUZE100_SW1CVOL, &value);
+		value &= ~0x3f;
+		value |= 0x23;
+		pmic_reg_write(p, PFUZE100_SW1CVOL, value);
+
+		finish_anatop_bypass();
+		printf("switch to ldo_bypass mode!\n");
+	}
+}
+#endif
+
+#ifdef CONFIG_CMD_BMODE
+static const struct boot_mode board_boot_modes[] = {
+	/* 4 bit bus width */
+	{"sd2",	 MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
+	{"sd3",	 MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
+	/* 8 bit bus width */
+	{"emmc", MAKE_CFGVAL(0x60, 0x58, 0x00, 0x00)},
+	{NULL,	 0},
+};
+#endif
+
+int board_late_init(void)
+{
+#ifdef CONFIG_CMD_BMODE
+	add_board_boot_modes(board_boot_modes);
+#endif
+
+#ifdef CONFIG_ENV_IS_IN_MMC
+	board_late_mmc_env_init();
+#endif
+	return 0;
+}
+
+int checkboard(void)
+{
+#ifdef CONFIG_SCMHVB
+	puts("Board: MX6DQSCM-HVB\n");
+#elif CONFIG_SCMEVB
+	puts("Board: MX6DQSCM-EVB\n");
+#elif CONFIG_QWKS_REV3
+	puts("Board: MX6DQSCM-QWKS-REV3\n");
+#else
+	puts("Board: MX6DQSCM-QWKS\n");
+#endif
+	return 0;
+}
+
+#ifdef CONFIG_FSL_FASTBOOT
+
+void board_fastboot_setup(void)
+{
+	switch (get_boot_device()) {
+#if defined(CONFIG_FASTBOOT_STORAGE_SATA)
+	case SATA_BOOT:
+		if (!getenv("fastboot_dev"))
+			setenv("fastboot_dev", "sata");
+		if (!getenv("bootcmd"))
+			setenv("bootcmd", "boota sata");
+		break;
+#endif /*CONFIG_FASTBOOT_STORAGE_SATA*/
+#if defined(CONFIG_FASTBOOT_STORAGE_MMC)
+	case SD2_BOOT:
+	case MMC2_BOOT:
+		if (!getenv("fastboot_dev"))
+			setenv("fastboot_dev", "mmc0");
+		if (!getenv("bootcmd"))
+			setenv("bootcmd", "boota mmc0");
+		break;
+	case SD3_BOOT:
+	case MMC3_BOOT:
+		if (!getenv("fastboot_dev"))
+			setenv("fastboot_dev", "mmc1");
+		if (!getenv("bootcmd"))
+			setenv("bootcmd", "boota mmc1");
+		break;
+	case MMC4_BOOT:
+		if (!getenv("fastboot_dev"))
+			setenv("fastboot_dev", "mmc2");
+		if (!getenv("bootcmd"))
+			setenv("bootcmd", "boota mmc2");
+		break;
+#endif /*CONFIG_FASTBOOT_STORAGE_MMC*/
+	default:
+		printf("unsupported boot devices\n");
+		break;
+	}
+}
+
+#ifdef CONFIG_ANDROID_RECOVERY
+
+#define GPIO_VOL_DN_KEY IMX_GPIO_NR(1, 5)
+iomux_v3_cfg_t const recovery_key_pads[] = {
+	(MX6_PAD_GPIO_5__GPIO1_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+};
+
+int check_recovery_cmd_file(void)
+{
+	int button_pressed = 0;
+	int recovery_mode = 0;
+
+	recovery_mode = recovery_check_and_clean_flag();
+#ifdef CONFIG_EVB_SETTINGS
+	/* Check Recovery Combo Button press or not. */
+	imx_iomux_v3_setup_multiple_pads(recovery_key_pads,
+					 ARRAY_SIZE(recovery_key_pads));
+
+	gpio_direction_input(GPIO_VOL_DN_KEY);
+
+	if (gpio_get_value(GPIO_VOL_DN_KEY) == 0) { /* VOL_DN is low assert */
+		button_pressed = 1;
+		printf("Recovery key pressed\n");
+	}
+#endif
+
+	return recovery_mode || button_pressed;
+}
+
+void board_recovery_setup(void)
+{
+	int bootdev = get_boot_device();
+
+	switch (bootdev) {
+#if defined(CONFIG_FASTBOOT_STORAGE_SATA)
+	case SATA_BOOT:
+		if (!getenv("bootcmd_android_recovery"))
+			setenv("bootcmd_android_recovery",
+			       "boota sata recovery");
+		break;
+#endif /*CONFIG_FASTBOOT_STORAGE_SATA*/
+#if defined(CONFIG_FASTBOOT_STORAGE_MMC)
+	case SD2_BOOT:
+	case MMC2_BOOT:
+		if (!getenv("bootcmd_android_recovery"))
+			setenv("bootcmd_android_recovery",
+			       "boota mmc0 recovery");
+		break;
+	case SD3_BOOT:
+	case MMC3_BOOT:
+		if (!getenv("bootcmd_android_recovery"))
+			setenv("bootcmd_android_recovery",
+			       "boota mmc1 recovery");
+		break;
+	case MMC4_BOOT:
+		if (!getenv("bootcmd_android_recovery"))
+			setenv("bootcmd_android_recovery",
+			       "boota mmc2 recovery");
+		break;
+#endif /*CONFIG_FASTBOOT_STORAGE_MMC*/
+	default:
+		printf("Unsupported bootup device for recovery: dev: %d\n",
+		       bootdev);
+		return;
+	}
+
+	printf("setup env for recovery..\n");
+	setenv("bootcmd", "run bootcmd_android_recovery");
+}
+
+#endif /*CONFIG_ANDROID_RECOVERY*/
+
+#endif /*CONFIG_FSL_FASTBOOT*/
diff --git a/board/freescale/mx6dqscm/plugin.S b/board/freescale/mx6dqscm/plugin.S
new file mode 100644
index 0000000..bd4f542
--- /dev/null
+++ b/board/freescale/mx6dqscm/plugin.S
@@ -0,0 +1,803 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <config.h>
+
+.macro imx6dq_scm_lpddr2_512mb_setting
+	ldr r0, =CCM_BASE_ADDR
+	ldr r1, =0xffffffff
+	str r1, [r0, #0x068]
+	ldr r1, =0xffffffff
+	str r1, [r0, #0x06c]
+	ldr r1, =0xffffffff
+	str r1, [r0, #0x070]
+	ldr r1, =0xffffffff
+	str r1, [r0, #0x074]
+	ldr r1, =0xffffffff
+	str r1, [r0, #0x078]
+	ldr r1, =0xffffffff
+	str r1, [r0, #0x07c]
+	ldr r1, =0xffffffff
+	str r1, [r0, #0x080]
+	ldr r1, =0xffffffff
+	str r1, [r0, #0x084]
+
+	/* DDR clock to 400MHz */
+	ldr r1, =0x00060324
+	str r1, [r0, #0x018]
+	/* AHB_ROOT_CLK change divide ratio from 4 to 3 for ENET */
+	ldr r1, =0x00018900
+	str r1, [r0, #0x014]
+
+	ldr r0, =IOMUXC_BASE_ADDR
+	ldr r1, =0x00080000
+	str r1, [r0, #0x798]
+	ldr r1, =0x00000000
+	str r1, [r0, #0x758]
+	ldr r1, =0x00000030
+
+	str r1, [r0, #0x588]
+	str r1, [r0, #0x594]
+
+	str r1, [r0, #0x56c]
+	str r1, [r0, #0x578]
+	str r1, [r0, #0x74c]
+
+	str r1, [r0, #0x57c]
+	ldr r1, =0x00000000
+	str r1, [r0, #0x58c]
+	ldr r1, =0x00000030
+	str r1, [r0, #0x59c]
+	str r1, [r0, #0x5a0]
+	str r1, [r0, #0x78c]
+
+	ldr r1, =0x00020000
+	str r1, [r0, #0x750]
+	ldr r1, =0x00003030
+	str r1, [r0, #0x5a8]
+	str r1, [r0, #0x5b0]
+	str r1, [r0, #0x524]
+	str r1, [r0, #0x51c]
+	str r1, [r0, #0x518]
+	str r1, [r0, #0x50c]
+	str r1, [r0, #0x5b8]
+	str r1, [r0, #0x5c0]
+
+	ldr r1, =0x00020000
+	str r1, [r0, #0x774]
+
+	ldr r1, =0x00000030
+	str r1, [r0, #0x784]
+	str r1, [r0, #0x788]
+	str r1, [r0, #0x794]
+	str r1, [r0, #0x79c]
+	str r1, [r0, #0x7a0]
+	str r1, [r0, #0x7a4]
+	str r1, [r0, #0x7a8]
+	str r1, [r0, #0x748]
+
+	str r1, [r0, #0x5ac]
+	str r1, [r0, #0x5b4]
+	str r1, [r0, #0x528]
+	str r1, [r0, #0x520]
+	str r1, [r0, #0x514]
+	str r1, [r0, #0x510]
+	str r1, [r0, #0x5bc]
+	str r1, [r0, #0x5c4]
+
+	ldr r1, =0x00000020
+	str r1, [r0, #0x590]
+	str r1, [r0, #0x598]
+
+
+	ldr r0, =MMDC_P0_BASE_ADDR
+
+	/* DDR setup */
+	ldr r2, =0x00008000
+	str r2, [r0, #0x1c]
+
+	/*SCM CONF*/
+	ldr r2, =0x1B4700C7
+	str r2, [r0, #0x85c]
+
+	ldr r2, =0xA1390003
+	str r2, [r0, #0x800]
+
+	/* calibration required */
+	ldr r2, =0x00400000
+	str r2, [r0, #0x890]
+
+	ldr r2, =0x44404044
+	str r2, [r0, #0x848]
+
+	ldr r2, =0x34343A38
+	str r2, [r0, #0x850]
+
+	ldr r2, =0x20000000
+	str r2, [r0, #0x83c]
+	ldr r2, =0x00000000
+	str r2, [r0, #0x840]
+
+	ldr r2, =0x33333333
+	str r2, [r0, #0x81c]
+	str r2, [r0, #0x820]
+	str r2, [r0, #0x824]
+	str r2, [r0, #0x828]
+	ldr r2, =0xf3333333
+	str r2, [r0, #0x82c]
+	str r2, [r0, #0x830]
+	str r2, [r0, #0x834]
+	str r2, [r0, #0x838]
+
+	ldr r2, =0x00000800
+	str r2, [r0, #0x8b8]
+
+	ldr r2, =0x00020036
+	str r2, [r0, #0x4]
+	ldr r2, =0x00000000
+	str r2, [r0, #0x8]
+	ldr r2, =0x33374133
+	str r2, [r0, #0xc]
+
+	ldr r2, =0x00100a82
+	str r2, [r0, #0x10]
+
+	ldr r2, =0x00000093
+	str r2, [r0, #0x14]
+
+	ldr r2, =0x0000174C
+	str r2, [r0, #0x18]
+	ldr r2, =0x00008000
+	str r2, [r0, #0x1c]
+	ldr r2, =0x0f9f26d2
+	str r2, [r0, #0x2c]
+	ldr r2, =0x00000010
+	str r2, [r0, #0x30]
+	ldr r2, =0x00190778
+	str r2, [r0, #0x38]
+
+	ldr r2, =0x0000004F
+	str r2, [r0, #0x40]
+
+	ldr r2, =0x83110000
+	str r2, [r0, #0x0]
+
+	/* Channel 0 */
+	ldr r2, =0x003F8030
+	str r2, [r0, #0x1c]
+	ldr r2, =0xFF0A8030
+	str r2, [r0, #0x1c]
+	ldr r2, =0x82018030
+	str r2, [r0, #0x1c]
+	ldr r2, =0x04028030
+	str r2, [r0, #0x1c]
+	ldr r2, =0x04038030
+	str r2, [r0, #0x1c]
+
+	ldr r2, =0xA1390003
+	str r2, [r0, #0x800]
+
+	ldr r2, =0x00001800
+	str r2, [r0, #0x20]
+
+	ldr r2, =0x00000000
+	str r2, [r0, #0x818]
+
+	ldr r2, =0x00025576
+	str r2, [r0, #0x4]
+
+	ldr r2, =0x00011006
+	str r2, [r0, #0x404]
+
+	ldr r2, =0x00000000
+	str r2, [r0, #0x1c]
+
+	ldr r0, =IOMUXC_BASE_ADDR
+	ldr r1, =0xF00000CF
+	str r1, [r0, #0x10]
+	ldr r1, =0x007F007F
+	str r1, [r0, #0x18]
+	ldr r1, =0x007F007F
+	str r1, [r0, #0x1c]
+.endm
+
+
+.macro imx6dq_scm_lpddr2_1gb_setting
+	ldr r0, =CCM_BASE_ADDR
+	ldr r1, =0xffffffff
+	str r1, [r0, #0x068]
+	ldr r1, =0xffffffff
+	str r1, [r0, #0x06c]
+	ldr r1, =0xffffffff
+	str r1, [r0, #0x070]
+	ldr r1, =0xffffffff
+	str r1, [r0, #0x074]
+	ldr r1, =0xffffffff
+	str r1, [r0, #0x078]
+	ldr r1, =0xffffffff
+	str r1, [r0, #0x07c]
+	ldr r1, =0xffffffff
+	str r1, [r0, #0x080]
+	ldr r1, =0xffffffff
+	str r1, [r0, #0x084]
+
+	/* DDR clock to 400MHz */
+	ldr r1, =0x00060324
+	str r1, [r0, #0x018]
+	/* AHB_ROOT_CLK change divide ratio from 4 to 3 for ENET */
+	ldr r1, =0x00018900
+	str r1, [r0, #0x014]
+
+	ldr r0, =IOMUXC_BASE_ADDR
+	ldr r1, =0x00080000
+	str r1, [r0, #0x798]
+	ldr r1, =0x00000000
+	str r1, [r0, #0x758]
+	ldr r1, =0x00000030
+
+	str r1, [r0, #0x588]
+	str r1, [r0, #0x594]
+
+	str r1, [r0, #0x56c]
+	str r1, [r0, #0x578]
+	str r1, [r0, #0x74c]
+
+	str r1, [r0, #0x57c]
+	ldr r1, =0x00000000
+	str r1, [r0, #0x58c]
+	ldr r1, =0x00000030
+	str r1, [r0, #0x59c]
+	str r1, [r0, #0x5a0]
+	str r1, [r0, #0x78c]
+
+	ldr r1, =0x00020000
+	str r1, [r0, #0x750]
+	ldr r1, =0x00003030
+	str r1, [r0, #0x5a8]
+	str r1, [r0, #0x5b0]
+	str r1, [r0, #0x524]
+	str r1, [r0, #0x51c]
+	str r1, [r0, #0x518]
+	str r1, [r0, #0x50c]
+	str r1, [r0, #0x5b8]
+	str r1, [r0, #0x5c0]
+
+	ldr r1, =0x00020000
+	str r1, [r0, #0x774]
+
+	ldr r1, =0x00000030
+	str r1, [r0, #0x784]
+	str r1, [r0, #0x788]
+	str r1, [r0, #0x794]
+	str r1, [r0, #0x79c]
+	str r1, [r0, #0x7a0]
+	str r1, [r0, #0x7a4]
+	str r1, [r0, #0x7a8]
+	str r1, [r0, #0x748]
+
+	str r1, [r0, #0x5ac]
+	str r1, [r0, #0x5b4]
+	str r1, [r0, #0x528]
+	str r1, [r0, #0x520]
+	str r1, [r0, #0x514]
+	str r1, [r0, #0x510]
+	str r1, [r0, #0x5bc]
+	str r1, [r0, #0x5c4]
+
+	ldr r1, =0x00000020
+	str r1, [r0, #0x590]
+	str r1, [r0, #0x598]
+
+
+	ldr r0, =MMDC_P0_BASE_ADDR
+	ldr r1, =MMDC_P1_BASE_ADDR
+
+	/* DDR setup */
+	ldr r2, =0x00008000
+	str r2, [r0, #0x1c]
+	str r2, [r1, #0x1c]
+
+	/*SCM CONF*/
+	ldr r2, =0x1B4700C7
+	str r2, [r0, #0x85c]
+	str r2, [r1, #0x85c]
+
+	ldr r2, =0xA1390003
+	str r2, [r0, #0x800]
+
+	/* calibration required */
+	ldr r2, =0x00400000
+	str r2, [r0, #0x890]
+	str r2, [r1, #0x890]
+
+	ldr r2, =0x44404044
+	str r2, [r0, #0x848]
+	ldr r2, =0x44443A46
+	str r2, [r1, #0x848]
+
+	ldr r2, =0x34343A38
+	str r2, [r0, #0x850]
+	ldr r2, =0x3E2E483C
+	str r2, [r1, #0x850]
+
+	ldr r2, =0x20000000
+	str r2, [r0, #0x83c]
+	ldr r2, =0x00000000
+	str r2, [r0, #0x840]
+	ldr r2, =0x20000000
+	str r2, [r1, #0x83c]
+	ldr r2, =0x00000000
+	str r2, [r1, #0x840]
+
+	ldr r2, =0x33333333
+	str r2, [r0, #0x81c]
+	str r2, [r0, #0x820]
+	str r2, [r0, #0x824]
+	str r2, [r0, #0x828]
+	str r2, [r1, #0x81c]
+	str r2, [r1, #0x820]
+	str r2, [r1, #0x824]
+	str r2, [r1, #0x828]
+	ldr r2, =0xf3333333
+	str r2, [r0, #0x82c]
+	str r2, [r0, #0x830]
+	str r2, [r0, #0x834]
+	str r2, [r0, #0x838]
+	str r2, [r1, #0x82c]
+	str r2, [r1, #0x830]
+	str r2, [r1, #0x834]
+	str r2, [r1, #0x838]
+
+	ldr r2, =0x00000800
+	str r2, [r0, #0x8b8]
+	str r2, [r1, #0x8b8]
+
+	ldr r2, =0x00020036
+	str r2, [r0, #0x4]
+	ldr r2, =0x00000000
+	str r2, [r0, #0x8]
+	ldr r2, =0x33374133
+	str r2, [r0, #0xc]
+
+	ldr r2, =0x00100a82
+	str r2, [r0, #0x10]
+
+	ldr r2, =0x00000093
+	str r2, [r0, #0x14]
+
+	ldr r2, =0x0000174C
+	str r2, [r0, #0x18]
+	ldr r2, =0x00008000
+	str r2, [r0, #0x1c]
+	ldr r2, =0x0f9f26d2
+	str r2, [r0, #0x2c]
+	ldr r2, =0x00000010
+	str r2, [r0, #0x30]
+	ldr r2, =0x00190778
+	str r2, [r0, #0x38]
+#ifdef CONFIG_INTERLEAVING_MODE
+	ldr r2, =0x00000053
+#else
+	ldr r2, =0x0000004F
+#endif
+	str r2, [r0, #0x40]
+
+	ldr r2, =0x83110000
+	str r2, [r0, #0x0]
+
+	ldr r2, =0x00020036
+	str r2, [r1, #0x4]
+	ldr r2, =0x00000000
+	str r2, [r1, #0x8]
+	ldr r2, =0x33374133
+	str r2, [r1, #0xc]
+	ldr r2, =0x00100a82
+	str r2, [r1, #0x10]
+	ldr r2, =0x00000093
+	str r2, [r1, #0x14]
+
+	ldr r2, =0x0000174C
+	str r2, [r1, #0x18]
+	ldr r2, =0x00008000
+	str r2, [r1, #0x1c]
+
+	ldr r2, =0x0f9f26d2
+	str r2, [r1, #0x2c]
+
+	ldr r2, =0x00000010
+	str r2, [r1, #0x30]
+
+	ldr r2, =0x00190778
+	str r2, [r1, #0x38]
+
+#ifdef CONFIG_INTERLEAVING_MODE
+	ldr r2, =0x00000013
+#else
+	ldr r2, =0x00000017
+#endif
+	str r2, [r1, #0x40]
+
+	ldr r2, =0x83110000
+	str r2, [r1, #0x0]
+
+	/* Channel 0 */
+	ldr r2, =0x003F8030
+	str r2, [r0, #0x1c]
+	ldr r2, =0xFF0A8030
+	str r2, [r0, #0x1c]
+	ldr r2, =0x82018030
+	str r2, [r0, #0x1c]
+	ldr r2, =0x04028030
+	str r2, [r0, #0x1c]
+	ldr r2, =0x04038030
+	str r2, [r0, #0x1c]
+
+	/* Channel 1 */
+	ldr r2, =0x003F8030
+	str r2, [r1, #0x1c]
+	ldr r2, =0xFF0A8030
+	str r2, [r1, #0x1c]
+	ldr r2, =0x82018030
+	str r2, [r1, #0x1c]
+	ldr r2, =0x04028030
+	str r2, [r1, #0x1c]
+	ldr r2, =0x04038030
+	str r2, [r1, #0x1c]
+
+	ldr r2, =0xA1390003
+	str r2, [r0, #0x800]
+
+	ldr r2, =0x00001800
+	str r2, [r0, #0x20]
+	str r2, [r1, #0x20]
+
+	ldr r2, =0x00000000
+	str r2, [r0, #0x818]
+	str r2, [r1, #0x818]
+
+	ldr r2, =0x00025576
+	str r2, [r0, #0x4]
+	str r2, [r1, #0x4]
+
+	ldr r2, =0x00011006
+	str r2, [r0, #0x404]
+	str r2, [r1, #0x404]
+
+	ldr r2, =0x00000000
+	str r2, [r0, #0x1c]
+	str r2, [r1, #0x1c]
+
+	ldr r0, =IOMUXC_BASE_ADDR
+	ldr r1, =0xF00000CF
+	str r1, [r0, #0x10]
+	ldr r1, =0x007F007F
+	str r1, [r0, #0x18]
+	ldr r1, =0x007F007F
+	str r1, [r0, #0x1c]
+.endm
+
+
+.macro imx6dq_scm_lpddr2_2gb_setting
+	ldr r0, =CCM_BASE_ADDR
+	ldr r1, =0xffffffff
+	str r1, [r0, #0x068]
+	ldr r1, =0xffffffff
+	str r1, [r0, #0x06c]
+	ldr r1, =0xffffffff
+	str r1, [r0, #0x070]
+	ldr r1, =0xffffffff
+	str r1, [r0, #0x074]
+	ldr r1, =0xffffffff
+	str r1, [r0, #0x078]
+	ldr r1, =0xffffffff
+	str r1, [r0, #0x07c]
+	ldr r1, =0xffffffff
+	str r1, [r0, #0x080]
+	ldr r1, =0xffffffff
+	str r1, [r0, #0x084]
+
+	/* DDR clock to 400MHz */
+	ldr r1, =0x00060324
+	str r1, [r0, #0x018]
+	/* AHB_ROOT_CLK change divide ratio from 4 to 3 for ENET */
+	ldr r1, =0x00018900
+	str r1, [r0, #0x014]
+
+	ldr r0, =IOMUXC_BASE_ADDR
+	ldr r1, =0x00080000
+	str r1, [r0, #0x798]
+	ldr r1, =0x00000000
+	str r1, [r0, #0x758]
+	ldr r1, =0x00000030
+
+	str r1, [r0, #0x588]
+	str r1, [r0, #0x594]
+
+	str r1, [r0, #0x56c]
+	str r1, [r0, #0x578]
+	str r1, [r0, #0x74c]
+
+	str r1, [r0, #0x57c]
+	ldr r1, =0x00000000
+	str r1, [r0, #0x58c]
+	ldr r1, =0x00000030
+	str r1, [r0, #0x59c]
+	str r1, [r0, #0x5a0]
+	str r1, [r0, #0x78c]
+
+	ldr r1, =0x00020000
+	str r1, [r0, #0x750]
+	ldr r1, =0x00003030
+	str r1, [r0, #0x5a8]
+	str r1, [r0, #0x5b0]
+	str r1, [r0, #0x524]
+	str r1, [r0, #0x51c]
+	str r1, [r0, #0x518]
+	str r1, [r0, #0x50c]
+	str r1, [r0, #0x5b8]
+	str r1, [r0, #0x5c0]
+
+	ldr r1, =0x00020000
+	str r1, [r0, #0x774]
+
+	ldr r1, =0x00000030
+	str r1, [r0, #0x784]
+	str r1, [r0, #0x788]
+	str r1, [r0, #0x794]
+	str r1, [r0, #0x79c]
+	str r1, [r0, #0x7a0]
+	str r1, [r0, #0x7a4]
+	str r1, [r0, #0x7a8]
+	str r1, [r0, #0x748]
+
+	str r1, [r0, #0x5ac]
+	str r1, [r0, #0x5b4]
+	str r1, [r0, #0x528]
+	str r1, [r0, #0x520]
+	str r1, [r0, #0x514]
+	str r1, [r0, #0x510]
+	str r1, [r0, #0x5bc]
+	str r1, [r0, #0x5c4]
+
+	ldr r1, =0x00000020
+	str r1, [r0, #0x590]
+	str r1, [r0, #0x598]
+
+
+	ldr r0, =MMDC_P0_BASE_ADDR
+	ldr r1, =MMDC_P1_BASE_ADDR
+
+	/* DDR setup */
+	ldr r2, =0x00008000
+	str r2, [r0, #0x1c]
+	str r2, [r1, #0x1c]
+
+	/*SCM CONF*/
+	ldr r2, =0x1B4700C7
+	str r2, [r0, #0x85c]
+	str r2, [r1, #0x85c]
+
+	ldr r2, =0xA1390003
+	str r2, [r0, #0x800]
+
+	/* calibration required */
+	ldr r2, =0x00400000
+	str r2, [r0, #0x890]
+	str r2, [r1, #0x890]
+
+	ldr r2, =0x44404044
+	str r2, [r0, #0x848]
+	ldr r2, =0x44443A46
+	str r2, [r1, #0x848]
+
+	ldr r2, =0x34343A38
+	str r2, [r0, #0x850]
+	ldr r2, =0x3E2E483C
+	str r2, [r1, #0x850]
+
+	ldr r2, =0x20000000
+	str r2, [r0, #0x83c]
+	ldr r2, =0x00000000
+	str r2, [r0, #0x840]
+	ldr r2, =0x20000000
+	str r2, [r1, #0x83c]
+	ldr r2, =0x00000000
+	str r2, [r1, #0x840]
+
+	ldr r2, =0x33333333
+	str r2, [r0, #0x81c]
+	str r2, [r0, #0x820]
+	str r2, [r0, #0x824]
+	str r2, [r0, #0x828]
+	str r2, [r1, #0x81c]
+	str r2, [r1, #0x820]
+	ldr r2, =0x00000000
+	str r2, [r1, #0x824]
+	ldr r2, =0x33333333
+	str r2, [r1, #0x828]
+	ldr r2, =0xf3333333
+	str r2, [r0, #0x82c]
+	str r2, [r0, #0x830]
+	str r2, [r0, #0x834]
+	str r2, [r0, #0x838]
+	str r2, [r1, #0x82c]
+	str r2, [r1, #0x830]
+	ldr r2, =0x00000000
+	str r2, [r1, #0x834]
+	ldr r2, =0xf3333333
+	str r2, [r1, #0x838]
+
+	ldr r2, =0x00000800
+	str r2, [r0, #0x8b8]
+	str r2, [r1, #0x8b8]
+
+	ldr r2, =0x00020036
+	str r2, [r0, #0x4]
+	ldr r2, =0x00000000
+	str r2, [r0, #0x8]
+	ldr r2, =0x33374133
+	str r2, [r0, #0xc]
+
+	ldr r2, =0x00100a82
+	str r2, [r0, #0x10]
+
+	ldr r2, =0x00000093
+	str r2, [r0, #0x14]
+
+	ldr r2, =0x0000174C
+	str r2, [r0, #0x18]
+	ldr r2, =0x00008000
+	str r2, [r0, #0x1c]
+	ldr r2, =0x0f9f26d2
+	str r2, [r0, #0x2c]
+	ldr r2, =0x009F0E10
+	str r2, [r0, #0x30]
+	ldr r2, =0x00190778
+	str r2, [r0, #0x38]
+#ifdef CONFIG_INTERLEAVING_MODE
+	ldr r2, =0x00000063
+#else
+	ldr r2, =0x0000005F
+#endif
+	str r2, [r0, #0x40]
+
+	ldr r2, =0xC3110000
+	str r2, [r0, #0x0]
+
+	ldr r2, =0x00020036
+	str r2, [r1, #0x4]
+	ldr r2, =0x00000000
+	str r2, [r1, #0x8]
+	ldr r2, =0x33374133
+	str r2, [r1, #0xc]
+	ldr r2, =0x00100a82
+	str r2, [r1, #0x10]
+	ldr r2, =0x00000093
+	str r2, [r1, #0x14]
+
+	ldr r2, =0x0000174C
+	str r2, [r1, #0x18]
+	ldr r2, =0x00008000
+	str r2, [r1, #0x1c]
+
+	ldr r2, =0x0f9f26d2
+	str r2, [r1, #0x2c]
+
+	ldr r2, =0x00000010
+	str r2, [r1, #0x30]
+
+	ldr r2, =0x00190778
+	str r2, [r1, #0x38]
+
+#ifdef CONFIG_INTERLEAVING_MODE
+	ldr r2, =0x00000023
+#else
+	ldr r2, =0x00000027
+#endif
+	str r2, [r1, #0x40]
+
+	ldr r2, =0xC3110000
+	str r2, [r1, #0x0]
+
+	/* Channel 0 */
+	/* CS0 */
+	ldr r2, =0x003F8030
+	str r2, [r0, #0x1c]
+	ldr r2, =0xFF0A8030
+	str r2, [r0, #0x1c]
+	ldr r2, =0x82018030
+	str r2, [r0, #0x1c]
+	ldr r2, =0x04028030
+	str r2, [r0, #0x1c]
+	ldr r2, =0x04038030
+	str r2, [r0, #0x1c]
+	/* CS1 */
+	ldr r2, =0x003F8038
+	str r2, [r0, #0x1c]
+	ldr r2, =0xFF0A8038
+	str r2, [r0, #0x1c]
+	ldr r2, =0x82018038
+	str r2, [r0, #0x1c]
+	ldr r2, =0x04028038
+	str r2, [r0, #0x1c]
+	ldr r2, =0x04038038
+	str r2, [r0, #0x1c]
+
+	/* Channel 1 */
+	/* CS0 */
+	ldr r2, =0x003F8030
+	str r2, [r1, #0x1c]
+	ldr r2, =0xFF0A8030
+	str r2, [r1, #0x1c]
+	ldr r2, =0x82018030
+	str r2, [r1, #0x1c]
+	ldr r2, =0x04028030
+	str r2, [r1, #0x1c]
+	ldr r2, =0x04038030
+	str r2, [r1, #0x1c]
+	/* CS1 */
+	ldr r2, =0x003F8038
+	str r2, [r1, #0x1c]
+	ldr r2, =0xFF0A8038
+	str r2, [r1, #0x1c]
+	ldr r2, =0x82018038
+	str r2, [r1, #0x1c]
+	ldr r2, =0x04028038
+	str r2, [r1, #0x1c]
+	ldr r2, =0x04038038
+	str r2, [r1, #0x1c]
+
+	ldr r2, =0xA1390003
+	str r2, [r0, #0x800]
+
+	ldr r2, =0x00001800
+	str r2, [r0, #0x20]
+	str r2, [r1, #0x20]
+
+	ldr r2, =0x00000000
+	str r2, [r0, #0x818]
+	str r2, [r1, #0x818]
+
+	ldr r2, =0x00025576
+	str r2, [r0, #0x4]
+	str r2, [r1, #0x4]
+
+	ldr r2, =0x00011006
+	str r2, [r0, #0x404]
+	str r2, [r1, #0x404]
+
+	ldr r2, =0x00000000
+	str r2, [r0, #0x1c]
+	str r2, [r1, #0x1c]
+
+	ldr r0, =IOMUXC_BASE_ADDR
+	ldr r1, =0xF00000CF
+	str r1, [r0, #0x10]
+	ldr r1, =0x007F007F
+	str r1, [r0, #0x18]
+	ldr r1, =0x007F007F
+	str r1, [r0, #0x1c]
+.endm
+
+
+.macro imx6_ddr_setting
+#if defined (CONFIG_SCM_LPDDR2_512MB)
+	imx6dq_scm_lpddr2_512mb_setting
+#elif defined (CONFIG_SCM_LPDDR2_2GB)
+	imx6dq_scm_lpddr2_2gb_setting
+#else
+	imx6dq_scm_lpddr2_1gb_setting
+#endif
+.endm
+
+.macro imx6_clock_gating
+.endm
+
+.macro imx6_qos_setting
+.endm
+
+/* include the common plugin code here */
+#include <asm/arch/mx6_plugin.S>