powerpc: 74xx_7xx: remove 74xx_7xx cpu support

All the 74xx_7xx boards are still non-generic boards:
P3G4, ZUMA, ppmc7xx, ELPPC, mpc7448hpc2

Acked-by: Marek Vasut <marex@denx.de>
Acked-by: Stefan Roese <sr@denx.de>
Acked-by: York Sun <yorksun@freescale.com>
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Nye Liu <nyet@zumanetworks.com>
Cc: Roy Zang <tie-fei.zang@freescale.com>

8 files changed, 0 insertions, 1864 deletions

diff --git a/board/freescale/mpc7448hpc2/Kconfig b/board/freescale/mpc7448hpc2/Kconfig
deleted file mode 100644
index 3e7f6e8..0000000
--- a/board/freescale/mpc7448hpc2/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_MPC7448HPC2
-
-config SYS_BOARD
-	default "mpc7448hpc2"
-
-config SYS_VENDOR
-	default "freescale"
-
-config SYS_CONFIG_NAME
-	default "mpc7448hpc2"
-
-endif
diff --git a/board/freescale/mpc7448hpc2/MAINTAINERS b/board/freescale/mpc7448hpc2/MAINTAINERS
deleted file mode 100644
index 9966b55..0000000
--- a/board/freescale/mpc7448hpc2/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-MPC7448HPC2 BOARD
-M:	Roy Zang <tie-fei.zang@freescale.com>
-S:	Maintained
-F:	board/freescale/mpc7448hpc2/
-F:	include/configs/mpc7448hpc2.h
-F:	configs/mpc7448hpc2_defconfig
diff --git a/board/freescale/mpc7448hpc2/Makefile b/board/freescale/mpc7448hpc2/Makefile
deleted file mode 100644
index 2cc211b..0000000
--- a/board/freescale/mpc7448hpc2/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# (C) Copyright 2000
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= mpc7448hpc2.o tsi108_init.o
-obj-y	+= asm_init.o
diff --git a/board/freescale/mpc7448hpc2/README b/board/freescale/mpc7448hpc2/README
deleted file mode 100644
index cbb043e..0000000
--- a/board/freescale/mpc7448hpc2/README
+++ /dev/null
@@ -1,184 +0,0 @@
-Freescale MPC7448hpc2 (Taiga) board
-===================================
-
-Created 08/11/2006 Roy Zang
---------------------------
-MPC7448hpc2 (Taiga) board is a high-performance PowerPC server reference
-design, which is optimized for high speed throughput between the processor and
-the memory, disk drive and Ethernet port subsystems.
-
-MPC7448hpc2(Taiga) is designed to the micro-ATX chassis, allowing it to be
-used in 1U or 2U rack-mount chassis¡¯, as well as in standard ATX/Micro-ATX
-chassis.
-
-Building U-Boot
-------------------
-The mpc7448hpc2 code base is known to compile using:
-	Binutils 2.15, Gcc 3.4.3, Glibc 2.3.3
-
-	$ make mpc7448hpc2_config
-	Configuring for mpc7448hpc2 board...
-
-	$ make
-
-Memory Map
-----------
-
-The memory map is setup for Linux to operate properly.
-
-The mapping is:
-
-	Range Start	Range End	Definition			Size
-
-	0x0000_0000	0x7fff_ffff	DDR				2G
-	0xe000_0000	0xe7ff_ffff	PCI Memory			128M
-	0xfa00_0000	0xfaff_ffff	PCI IO				16M
-	0xfb00_0000	0xfbff_ffff	PCI Config			16M
-	0xfc00_0000	0xfc0f_ffff	NVRAM/CADMUS			1M
-	0xfe00_0000	0xfeff_ffff	PromJet				16M
-	0xff00_0000	0xff80_0000	FLASH (boot flash)		8M
-	0xff80_0000	0xffff_ffff	FLASH (second half flash)	8M
-
-Using Flash
------------
-
-The MPC7448hpc2 board has two "banks" of flash, each 8MB in size
-(2^23 = 0x00800000).
-
-Note: the "bank" here refers to half of the flash. In fact, there is only one
-bank of flash, which is divided into low and high half. Each is controlled by
-the most significant bit of the address bus. The so called "bank" is only for
-convenience.
-
-There is a switch which allows the "bank" to be selected.  The switch
-settings for updating flash are given below.
-
-The u-boot commands for copying the boot-bank into the secondary bank are
-as follows:
-
-	erase ff800000 ff880000
-	cp.b ff000000 ff800000 80000
-
-U-boot commands for downloading an image via tftp and flashing
-it into the secondary bank:
-
-	tftp 10000 <u-boot.bin.image>
-	erase ff000000 ff080000
-	cp.b 10000 ff000000 80000
-
-After copying the image into the second bank of flash, be sure to toggle
-SW3[4] on board before resetting the board in order to set the
-secondary bank as the boot-bank.
-
-Board Switches
-----------------------
-
-Most switches on the board should not be changed.  The most frequent
-user-settable switches on the board are used to configure
-the flash banks and determining the PCI frequency.
-
-SW1[1-5]: Processor core voltage
-
-	12345		Core Voltage
-	-----
-	SW1=01111	1.000V.
-	SW1=01101	1.100V.
-	SW1=01011	1.200V.
-	SW1=01001	1.300V only for MPC7447A.
-
-
-SW2[1-6]: CPU core frequency
-
-		CPU Core Frequency (MHz)
-			Bus Frequency
-	123456		100	133	167	200	Ratio
-
-	------
-	SW2=101100	500	667	833	1000	5x
-	SW2=100100	550	733	917	1100	5.5x
-	SW2=110100	600	800	1000	1200	6x
-	SW2=010100	650	866	1083	1300	6.5x
-	SW2=001000	700	930	1167	1400	7x
-	SW2=000100	750	1000	1250	1500	7.5x
-	SW2=110000	800	1066	1333	1600	8x
-	SW2=011000	850	1333	1417	1700	8.5x only for MPC7447A
-	SW2=011110	900	1200	1500	1800	9x
-
-This table shows only a subset of available frequency options; see the CPU
-hardware specifications for more information.
-
-SW2[7-8]: Bus Protocol and CPU Reset Option
-
-	7
-	-
-	SW2=0		System bus uses MPX bus protocol
-	SW2=1		System bus uses 60x bus protocol
-
-	8
-	-
-	SW2=0		TSI108 can cause CPU reset
-	SW2=1		TSI108 can not cause CPU reset
-
-SW3[1-8] system options
-
-	123
-	---
-	SW3=xxx		Connected to GPIO[0:2] on TSI108
-
-	4
-	-
-	SW3=0		CPU boots from low half of flash
-	SW3=1		CPU boots from high half of flash
-
-	5
-	-
-	SW3=0		SATA and slot2 connected to PCI bus
-	SW3=1		Only slot1 connected to PCI bus
-
-	6
-	-
-	SW3=0		USB connected to PCI bus
-	SW3=1		USB disconnected from PCI bus
-
-	7
-	-
-	SW3=0		Flash is write protected
-	SW3=1		Flash is NOT write protected
-
-	8
-	-
-	SW3=0		CPU will boot from flash
-	SW3=1		CPU will boot from PromJet
-
-SW4[1-3]: System bus frequency
-
-			Bus Frequency (MHz)
-	---
-	SW4=010			183
-	SW4=011			100
-	SW4=100			133
-	SW4=101			166 only for MPC7447A
-	SW4=110			200 only for MPC7448
-	others			reserved
-
-SW4[4-6]: DDR2 SDRAM frequency
-
-			Bus Frequency (MHz)
-	---
-	SW4=000		external clock
-	SW4=011		system clock
-	SW4=100		133
-	SW4=101		166
-	SW4=110		200
-	others		reserved
-
-SW4[7-8]: PCI/PCI-X frequency control
-	7
-	-
-	SW4=0		PCI/PCI-X bus operates normally
-	SW4=1		PCI bus forced to PCI-33 mode
-
-	8
-	-
-	SW4=0		PCI-X mode at 133 MHz allowed
-	SW4=1		PCI-X mode limited to 100 MHz
diff --git a/board/freescale/mpc7448hpc2/asm_init.S b/board/freescale/mpc7448hpc2/asm_init.S
deleted file mode 100644
index 70315c3..0000000
--- a/board/freescale/mpc7448hpc2/asm_init.S
+++ /dev/null
@@ -1,905 +0,0 @@
-/*
- * (C) Copyright 2004-05;  Tundra Semiconductor Corp.
- *
- * Added automatic detect of SDC settings
- * Copyright (c) 2005 Freescale Semiconductor, Inc.
- * Maintainer tie-fei.zang@freescale.com
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*
- * FILENAME: asm_init.s
- *
- * Originator: Alex Bounine
- *
- * DESCRIPTION:
- * Initialization code for the Tundra Tsi108 bridge chip
- *
- */
-
-#include <config.h>
-#include <version.h>
-
-#include <ppc_asm.tmpl>
-#include <ppc_defs.h>
-#include <asm/processor.h>
-
-#include <tsi108.h>
-
-/*
- * Build Configuration Options
- */
-
-/* #define DISABLE_PBM		disables usage of PB Master */
-/* #define SDC_HARDCODED_INIT	config SDRAM controller with hardcoded values */
-/* #define SDC_AUTOPRECH_EN	enable SDRAM auto precharge */
-
-/*
- * Hardcoded SDC settings
- */
-
-#ifdef SDC_HARDCODED_INIT
-
-/* Micron MT9HTF6472AY-40EA1 : Unbuffered, 512MB, 400, CL3, Single Rank */
-
-#define VAL_SD_REFRESH	(0x61A)
-#define VAL_SD_TIMING	(0x0308336b)
-#define VAL_SD_D0_CTRL	(0x07100021)	/* auto-precharge disabled */
-#define VAL_SD_D0_BAR	(0x0FE00000)	/* 512MB @ 0x00000000 */
-#define VAL_SD_D1_CTRL	(0x07100021)	/* auto-precharge disabled */
-#define VAL_SD_D1_BAR	(0x0FE00200)	/* 512MB @ 0x20000000 */
-
-#endif /* SDC_HARDCODED_INIT */
-
-/*
- CPU Configuration:
-
- CPU Address and Data Parity enables.
-
-#define CPU_AP
-#define CPU_DP
-*/
-
-/*
- * Macros
- * !!! Attention !!! Macros LOAD_PTR, LOAD_U32 and LOAD_MEM defined below are
- * expected to work correctly for the CSR space within 32KB range.
- *
- * LOAD_PTR and LOAD_U32 - load specified register with a 32 bit constant.
- * These macros are absolutely identical except their names. This difference
- * is provided intentionally for better readable code.
- */
-
-#define LOAD_PTR(reg,const32) \
-	addis reg,r0,const32@h; ori reg,reg,const32@l
-
-#define LOAD_U32(reg,const32) \
-	addis reg,r0,const32@h; ori reg,reg,const32@l
-
-/* LOADMEM initializes a register with the contents of a specified 32-bit
- * memory location, usually a CSR value.
- */
-
-#define LOAD_MEM(reg,addr32) \
-	addis reg,r0,addr32@ha; lwz reg,addr32@l(reg)
-
-#ifndef SDC_HARDCODED_INIT
-sdc_clk_sync:
-	/* MHz: 0,0,183,100,133,167,200,233 */
-	.long	0, 0, 6, 10, 8, 6, 5, 4		/* nSec */
-#endif
-
-/*
- * board_asm_init() - early initialization function. Coded to be portable to
- * dual-CPU configuration.
- * Checks CPU number and performs board HW initialization if called for CPU0.
- * Registers used: r3,r4,r5,r6,r19,r29
- *
- * NOTE: For dual-CPU configuration only CPU0 is allowed to configure Tsi108
- * and the rest of the board. Current implementation demonstrates two
- * possible ways to identify CPU number:
- * - for MPC74xx platform: uses MSSCR0[ID] bit as defined in UM.
- * - for PPC750FX/GX boards: uses WHO_AM_I bit reported by Tsi108.
- */
-
-	.globl board_asm_init
-board_asm_init:
-	mflr	r19	/* Save LR to be able return later. */
-	bl	icache_enable	/* Enable icache to reduce reads from flash. */
-
-/* Initialize pointer to Tsi108 register space */
-
-	LOAD_PTR(r29,CONFIG_SYS_TSI108_CSR_RST_BASE)/* r29 - pointer to tsi108 CSR space */
-	ori r4,r29,TSI108_PB_REG_OFFSET
-
-/* Check Processor Version Number */
-
-	mfspr	r3, PVR
-	rlwinm	r3,r3,16,16,23	/* get ((Processor Version Number) & 0xFF00) */
-
-	cmpli	0,0,r3,0x8000	/* MPC74xx */
-	bne	cont_brd_init
-
-	/*
-	 * For MPC744x/5x enable extended BATs[4-7]
-	 * Sri: Set HIGH_BAT_EN and XBSEN, and SPD =1
-	 * to disable prefetch
-	 */
-
-	mfspr	r5, HID0
-	oris	r5, r5, 0x0080	/* Set HID0[HIGH_BAT_EN] bit #8 */
-	ori	r5, r5, 0x0380	/* Set SPD,XBSEN,SGE bits #22,23,24 */
-	mtspr	HID0, r5
-	isync
-	sync
-
-	/* Adding code to disable external interventions in MPX bus mode */
-	mfspr	r3, 1014
-	oris	r3, r3, 0x0100	/* Set the EIDIS bit in MSSCR0:  bit 7 */
-	mtspr	1014, r3
-	isync
-	sync
-
-	/* Sri: code to enable FP unit */
-	mfmsr	r3
-	ori	r3, r3, 0x2000
-	mtmsr	r3
-	isync
-	sync
-
-	/* def CONFIG_DUAL_CPU
-	 * For MPC74xx processor, use MSSCR0[ID] bit to identify CPU number.
-	 */
-#if(1)
-	mfspr	r3,1014		/* read MSSCR0 */
-	rlwinm.	r3,r3,27,31,31	/* get processor ID number */
-	mtspr	SPRN_PIR,r3	/* Save CPU ID */
-	sync
-	bne	init_done
-	b	do_tsi108_init
-
-cont_brd_init:
-
-	/* An alternative method of checking the processor number (in addition
-	 * to configuration using MSSCR0[ID] bit on MPC74xx).
-	 * Good for IBM PPC750FX/GX.
-	 */
-
-	lwz	r3,PB_BUS_MS_SELECT(r4)	/* read PB_ID register */
-	rlwinm.	r3,r3,24,31,31		/* get processor ID number */
-	bne init_done
-#else
-
-cont_brd_init:
-
-#endif /* CONFIG_DUAL_CPU */
-
-	/* Initialize Tsi108 chip */
-
-do_tsi108_init:
-
-	/*
-	 * Adjust HLP/Flash parameters. By default after reset the HLP port is
-	 * set to support slow devices. Better performance can be achived when
-	 * an optimal parameters are used for specific EPROM device.
-	 * NOTE: This should be performed ASAP for the emulation platform
-	 * because it has 5MHz HLP clocking.
-	 */
-
-#ifdef CONFIG_TSI108EMU
-	ori	r4,r29,TSI108_HLP_REG_OFFSET
-	LOAD_U32(r5,0x434422c0)
-	stw	r5,0x08(r4)	/* set HLP B0_CTRL0 */
-	sync
-	LOAD_U32(r5,0xd0012000)
-	stw	r5,0x0c(r4)		/* set HLP B0_CTRL1 */
-	sync
-#endif
-
-	/* Initialize PB interface. */
-
-	ori r4,r29,TSI108_PB_REG_OFFSET
-
-#if (CONFIG_SYS_TSI108_CSR_BASE != CONFIG_SYS_TSI108_CSR_RST_BASE)
-	/* Relocate (if required) Tsi108 registers. Set new value for
-	 * PB_REG_BAR:
-	 * Note we are in the 32-bit address mode.
-	 */
-	LOAD_U32(r5,(CONFIG_SYS_TSI108_CSR_BASE | 0x01)) /* PB_REG_BAR: BA + EN */
-	stw	r5,PB_REG_BAR(r4)
-	andis.	r29,r5,0xFFFF
-	sync
-	ori	r4,r29,TSI108_PB_REG_OFFSET
-#endif
-
-	/* Set PB Slave configuration register */
-
-	LOAD_U32(r5,0x00002481)	/* PB_SCR: TEA enabled,AACK delay = 1 */
-	lwz	r3, PB_RSR(r4)	/* get PB bus mode */
-	xori	r3,r3,0x0001	/* mask PB_BMODE: r3 -> (0 = 60X, 1 = MPX) */
-	rlwimi  r5,r3,14,17,17	/* for MPX: set DTI_MODE bit */
-	stw	r5,PB_SCR(r4)
-	sync
-
-	/* Configure PB Arbiter */
-
-	lwz	r5,PB_ARB_CTRL(r4)	/* Read PB Arbiter Control Register */
-	li	r3, 0x00F0		/* ARB_PIPELINE_DEP mask */
-#ifdef DISABLE_PBM
-	ori	r3,r3,0x1000	/* add PBM_EN to clear (enabled by default) */
-#endif
-	andc	r5,r5,r3	/* Clear the masked bit fields */
-	ori	r5,r5,0x0001	/* Set pipeline depth */
-	stw	r5,PB_ARB_CTRL(r4)
-
-#if (0)	/* currently using the default settings for PBM after reset */
-	LOAD_U32(r5,0x)		/* value for PB_MCR */
-	stw	r5,PB_MCR(r4)
-	sync
-
-	LOAD_U32(r5,0x)		/* value for PB_MCMD */
-	stw	r5,PB_MCMD(r4)
-	sync
-#endif
-
-	/* Disable or enable PVT based on processor bus frequency
-	 * 1. Read CG_PWRUP_STATUS register field bits 18,17,16
-	 * 2. See if the value is < or > 133mhz (18:16 = 100)
-	 * 3. If > enable PVT
-	 */
-
-	LOAD_U32(r3,0xC0002234)
-	lwz	r3,0(r3)
-	rlwinm	r3,r3,16,29,31
-
-	cmpi	0,0,r3,0x0004
-	bgt	sdc_init
-
-#ifndef CONFIG_TSI108EMU
-	/* FIXME: Disable PB calibration control for any real Tsi108 board */
-	li	r5,0x0101	/* disable calibration control */
-	stw	r5,PB_PVT_CTRL2(r4)
-	sync
-#endif
-
-	/* Initialize SDRAM controller. */
-
-sdc_init:
-
-#ifndef SDC_HARDCODED_INIT
-	/* get SDC clock prior doing sdram controller autoconfig */
-	ori	r4,r29,TSI108_CLK_REG_OFFSET	/* r4 - ptr to CG registers */
-	lwz	r3, CG_PWRUP_STATUS(r4)		/* get CG configuration */
-	rlwinm	r3,r3,12,29,31			/* r3 - SD clk */
-	lis	r5,sdc_clk_sync@h
-	ori	r5,r5,sdc_clk_sync@l
-	/* Sri:  At this point check if r3 = 001. If yes,
-	 * the memory frequency should be same as the
-	 * MPX bus frequency
-	 */
-	cmpi	0,0,r3,0x0001
-	bne	get_nsec
-	lwz	r6, CG_PWRUP_STATUS(r4)
-	rlwinm	r6,r6,16,29,31
-	mr	r3,r6
-
-get_nsec:
-	rlwinm	r3,r3,2,0,31
-	lwzx	r9,r5,r3	/* get SD clk rate in nSec */
-	/* ATTN: r9 will be used by SPD routine */
-#endif /* !SDC_HARDCODED_INIT */
-
-	ori	r4,r29,TSI108_SD_REG_OFFSET /* r4 - ptr to SDRAM registers */
-
-	/* Initialize SDRAM controller. SDRAM Size = 512MB, One DIMM. */
-
-	LOAD_U32(r5,0x00)
-	stw	r5,SD_INT_ENABLE(r4) /* Ensure that interrupts are disabled */
-#ifdef ENABLE_SDRAM_ECC
-	li	r5, 0x01
-#endif /* ENABLE_SDRAM_ECC */
-	stw	r5,SD_ECC_CTRL(r4)	/* Enable/Disable ECC */
-	sync
-
-#ifdef SDC_HARDCODED_INIT /* config sdram controller with hardcoded values */
-
-	/* First read the CG_PWRUP_STATUS register to get the
-	 * memory speed from bits 22,21,20
-	 */
-
-	LOAD_U32(r3,0xC0002234)
-	lwz	r3,0(r3)
-	rlwinm	r3,r3,12,29,31
-
-	/* Now first check for 166, then 200, or default */
-
-	cmpi	0,0,r3,0x0005
-	bne	check_for_200mhz
-
-	/* set values for 166 Mhz memory speed
-	 * Set refresh rate and timing parameters
-	 */
-	LOAD_U32(r5,0x00000515)
-	stw	r5,SD_REFRESH(r4)
-	LOAD_U32(r5,0x03073368)
-	stw	r5,SD_TIMING(r4)
-	sync
-
-	/* Initialize DIMM0 control and BAR registers */
-	LOAD_U32(r5,VAL_SD_D0_CTRL)	/* auto-precharge disabled */
-#ifdef SDC_AUTOPRECH_EN
-	oris	r5,r5,0x0001		/* set auto precharge EN bit */
-#endif
-	stw	r5,SD_D0_CTRL(r4)
-	LOAD_U32(r5,VAL_SD_D0_BAR)
-	stw	r5,SD_D0_BAR(r4)
-	sync
-
-	/* Initialize DIMM1 control and BAR registers
-	 * (same as dimm 0, next 512MB, disabled)
-	 */
-	LOAD_U32(r5,VAL_SD_D1_CTRL)	/* auto-precharge disabled */
-#ifdef SDC_AUTOPRECH_EN
-	oris	r5,r5,0x0001	/* set auto precharge EN bit */
-#endif
-	stw	r5,SD_D1_CTRL(r4)
-	LOAD_U32(r5,VAL_SD_D1_BAR)
-	stw	r5,SD_D1_BAR(r4)
-	sync
-
-	b	sdc_init_done
-
-check_for_200mhz:
-
-	cmpi	0,0,r3,0x0006
-	bne	set_default_values
-
-	/* set values for 200Mhz memory speed
-	 * Set refresh rate and timing parameters
-	 */
-	LOAD_U32(r5,0x0000061a)
-	stw	r5,SD_REFRESH(r4)
-	LOAD_U32(r5,0x03083348)
-	stw	r5,SD_TIMING(r4)
-	sync
-
-	/* Initialize DIMM0 control and BAR registers */
-	LOAD_U32(r5,VAL_SD_D0_CTRL)	/* auto-precharge disabled */
-#ifdef SDC_AUTOPRECH_EN
-	oris	r5,r5,0x0001		/* set auto precharge EN bit */
-#endif
-	stw	r5,SD_D0_CTRL(r4)
-	LOAD_U32(r5,VAL_SD_D0_BAR)
-	stw	r5,SD_D0_BAR(r4)
-	sync
-
-	/* Initialize DIMM1 control and BAR registers
-	 * (same as dimm 0, next 512MB, disabled)
-	 */
-	LOAD_U32(r5,VAL_SD_D1_CTRL)	/* auto-precharge disabled */
-#ifdef SDC_AUTOPRECH_EN
-	oris	r5,r5,0x0001		/* set auto precharge EN bit */
-#endif
-	stw	r5,SD_D1_CTRL(r4)
-	LOAD_U32(r5,VAL_SD_D1_BAR)
-	stw	r5,SD_D1_BAR(r4)
-	sync
-
-	b	sdc_init_done
-
-set_default_values:
-
-	/* Set refresh rate and timing parameters */
-	LOAD_U32(r5,VAL_SD_REFRESH)
-	stw	r5,SD_REFRESH(r4)
-	LOAD_U32(r5,VAL_SD_TIMING)
-	stw	r5,SD_TIMING(r4)
-	sync
-
-	/* Initialize DIMM0 control and BAR registers */
-	LOAD_U32(r5,VAL_SD_D0_CTRL)	/* auto-precharge disabled */
-#ifdef SDC_AUTOPRECH_EN
-	oris	r5,r5,0x0001		/* set auto precharge EN bit */
-#endif
-	stw	r5,SD_D0_CTRL(r4)
-	LOAD_U32(r5,VAL_SD_D0_BAR)
-	stw	r5,SD_D0_BAR(r4)
-	sync
-
-	/* Initialize DIMM1 control and BAR registers
-	 * (same as dimm 0, next 512MB, disabled)
-	 */
-	LOAD_U32(r5,VAL_SD_D1_CTRL)	/* auto-precharge disabled */
-#ifdef SDC_AUTOPRECH_EN
-	oris	r5,r5,0x0001		/* set auto precharge EN bit */
-#endif
-	stw	r5,SD_D1_CTRL(r4)
-	LOAD_U32(r5,VAL_SD_D1_BAR)
-	stw	r5,SD_D1_BAR(r4)
-	sync
-#else /* !SDC_HARDCODED_INIT */
-	bl	tsi108_sdram_spd	/* automatically detect SDC settings */
-#endif /* SDC_HARDCODED_INIT */
-
-sdc_init_done:
-
-#ifdef DISABLE_PBM
-	LOAD_U32(r5,0x00000030)		/* PB_EN + OCN_EN */
-#else
-	LOAD_U32(r5,0x00000230)		/* PB_EN + OCN_EN + PB/OCN=80/20 */
-#endif /* DISABLE_PBM */
-
-#ifdef CONFIG_TSI108EMU
-	oris	r5,r5,0x0010		/* set EMULATION_MODE bit */
-#endif
-
-	stw	r5,SD_CTRL(r4)
-	eieio
-	sync
-
-	/* Enable SDRAM access */
-
-	oris	r5,r5,0x8000		/* start SDC: set SD_CTRL[ENABLE] bit */
-	stw	r5,SD_CTRL(r4)
-	sync
-
-wait_init_complete:
-	lwz	r5,SD_STATUS(r4)
-	andi.	r5,r5,0x0001
-	/* wait until SDRAM initialization is complete */
-	beq	wait_init_complete
-
-	/* Map SDRAM into the processor bus address space */
-
-	ori	r4,r29,TSI108_PB_REG_OFFSET
-
-	/* Setup BARs associated with direct path PB<->SDRAM */
-
-	/* PB_SDRAM_BAR1:
-	 * provides a direct path to the main system memory (cacheable SDRAM)
-	 */
-
-	/* BA=0,Size=512MB, ENable, No Addr.Translation */
-	LOAD_U32(r5, 0x00000011)
-	stw	r5,PB_SDRAM_BAR1(r4)
-	sync
-
-	/* Make sure that PB_SDRAM_BAR1 decoder is set
-	 * (to allow following immediate read from SDRAM)
-	 */
-	lwz	r5,PB_SDRAM_BAR1(r4)
-	sync
-
-	/* PB_SDRAM_BAR2:
-	 * provides non-cacheable alias (via the direct path) to main
-	 * system memory.
-	 * Size = 512MB, ENable, Addr.Translation - ON,
-	 * BA = 0x0_40000000, TA = 0x0_00000000
-	 */
-
-	LOAD_U32(r5, 0x40010011)
-	stw	r5,PB_SDRAM_BAR2(r4)
-	sync
-
-	/* Make sure that PB_SDRAM_BAR2 decoder is set
-	 * (to allow following immediate read from SDRAM)
-	 */
-	lwz	r5,PB_SDRAM_BAR2(r4)
-	sync
-
-init_done:
-
-	/* All done. Restore LR and return. */
-	mtlr	r19
-	blr
-
-#if (0)
-	/*
-	 * init_cpu1
-	 * This routine enables CPU1 on the dual-processor system.
-	 * Now there is only one processor in the system
-	 */
-
-	.global enable_cpu1
-enable_cpu1:
-
-	lis	r3,Tsi108_Base@ha	/* Get Grendel CSR Base Addr */
-	addi	r3,r3,Tsi108_Base@l
-	lwz	r3,0(r3)		/* R3 = CSR Base Addr */
-	ori	r4,r3,TSI108_PB_REG_OFFSET
-	lwz	r3,PB_ARB_CTRL(r4)	/* Read PB Arbiter Control Register */
-	ori	r3,r3,0x0200		/* Set M1_EN bit */
-	stw	r3,PB_ARB_CTRL(r4)
-
-	blr
-#endif
-
-	/*
-	 * enable_EI
-	 * Enable CPU core external interrupt
-	 */
-
-	.global	enable_EI
-enable_EI:
-	mfmsr	r3
-	ori	r3,r3,0x8000	/* set EE bit */
-	mtmsr	r3
-	blr
-
-	/*
-	 * disable_EI
-	 * Disable CPU core external interrupt
-	 */
-
-	.global disable_EI
-disable_EI:
-	mfmsr	r3
-	li	r4,-32768	/* aka "li  r4,0x8000" */
-	andc	r3,r3,r4	/* clear EE bit */
-	mtmsr	r3
-	blr
-
-#ifdef ENABLE_SDRAM_ECC
-	/* enables SDRAM ECC  */
-
-	.global	enable_ECC
-enable_ECC:
-	ori	r4,r29,TSI108_SD_REG_OFFSET
-	lwz	r3,SD_ECC_CTRL(r4)	/* Read SDRAM ECC Control Register */
-	ori	r3,r3,0x0001		/* Set ECC_EN bit */
-	stw	r3,SD_ECC_CTRL(r4)
-	blr
-
-	/*
-	 * clear_ECC_err
-	 * Clears all pending SDRAM ECC errors
-	 * (normally after SDRAM scrubbing/initialization)
-	 */
-
-	.global	clear_ECC_err
-clear_ECC_err:
-	ori r4,r29,TSI108_SD_REG_OFFSET
-	ori r3,r0,0x0030	/* ECC_UE_INT + ECC_CE_INT bits */
-	stw r3,SD_INT_STATUS(r4)
-	blr
-
-#endif /* ENABLE_SDRAM_ECC */
-
-#ifndef SDC_HARDCODED_INIT
-
-	/* SDRAM SPD Support */
-#define	SD_I2C_CTRL1	(0x400)
-#define	SD_I2C_CTRL2	(0x404)
-#define SD_I2C_RD_DATA	(0x408)
-#define SD_I2C_WR_DATA	(0x40C)
-
-	/*
-	 * SDRAM SPD Support Macros
-	 */
-
-#define SPD_DIMM0	(0x00000100)
-#define SPD_DIMM1	(0x00000200)	/* SPD_DIMM1 was 0x00000000 */
-
-#define SPD_RDIMM			(0x01)
-#define SPD_UDIMM			(0x02)
-
-#define SPD_CAS_3			0x8
-#define SPD_CAS_4			0x10
-#define SPD_CAS_5			0x20
-
-#define ERR_NO_DIMM_FOUND		(0xdb0)
-#define ERR_TRAS_FAIL			(0xdb1)
-#define ERR_TRCD_FAIL			(0xdb2)
-#define ERR_TRP_FAIL			(0xdb3)
-#define ERR_TWR_FAIL			(0xdb4)
-#define ERR_UNKNOWN_PART		(0xdb5)
-#define ERR_NRANK_INVALID		(0xdb6)
-#define ERR_DIMM_SIZE			(0xdb7)
-#define ERR_ADDR_MODE			(0xdb8)
-#define ERR_RFRSH_RATE			(0xdb9)
-#define ERR_DIMM_TYPE			(0xdba)
-#define ERR_CL_VALUE			(0xdbb)
-#define ERR_TRFC_FAIL			(0xdbc)
-
-/* READ_SPD requirements:
- * byte - byte address in SPD device (0 - 255)
- * r3 = will return data read from I2C Byte location
- * r4 - unchanged (SDC base addr)
- * r5 - clobbered in routine (I2C status)
- * r10 - number of DDR slot where first SPD device is detected
- */
-
-#define READ_SPD(byte_num)		\
-	addis	r3, 0, byte_num@l;	\
-	or	r3, r3, r10;		\
-	ori	r3, r3, 0x0A;		\
-	stw	r3, SD_I2C_CTRL1(r4);	\
-	li	r3, I2C_CNTRL2_START;	\
-	stw	r3, SD_I2C_CTRL2(r4);	\
-	eieio;				\
-	sync;				\
-	li	r3, 0x100;		\
-1:;					\
-	addic.	r3, r3, -1;		\
-	bne	1b;			\
-2:;					\
-	lwz	r5, SD_I2C_CTRL2(r4);	\
-	rlwinm.	r3,r5,0,23,23;		\
-	bne	2b;			\
-	rlwinm.	r3,r5,0,3,3;		\
-	lwz	r3,SD_I2C_RD_DATA(r4)
-
-#define SPD_MIN_RFRSH	(0x80)
-#define SPD_MAX_RFRSH	(0x85)
-
-refresh_rates:	/* in nSec */
-	.long	15625	/* Normal (0x80) */
-	.long	3900	/* Reduced 0.25x (0x81) */
-	.long	7800	/* Reduced 0.5x (0x82) */
-	.long	31300	/* Extended 2x (0x83) */
-	.long	62500	/* Extended 4x (0x84) */
-	.long	125000	/* Extended 8x (0x85) */
-
-/*
- * tsi108_sdram_spd
- *
- * Inittializes SDRAM Controller using DDR2 DIMM Serial Presence Detect data
- * Uses registers: r4 - SDC base address (not changed)
- *				   r9 - SDC clocking period in nSec
- * Changes registers: r3,r5,r6,r7,r8,r10,r11
- */
-
-tsi108_sdram_spd:
-
-	li	r10,SPD_DIMM0
-	xor	r11,r11,r11		/* DIMM Base Address: starts from 0 */
-
-do_first_dimm:
-
-	/* Program Refresh Rate	Register */
-
-	READ_SPD(12)			/* get Refresh Rate */
-	beq	check_next_slot
-	li	r5, ERR_RFRSH_RATE
-	cmpi	0,0,r3,SPD_MIN_RFRSH
-	ble	spd_fail
-	cmpi	0,0,r3,SPD_MAX_RFRSH
-	bgt	spd_fail
-	addi	r3,r3,-SPD_MIN_RFRSH
-	rlwinm	r3,r3,2,0,31
-	lis	r5,refresh_rates@h
-	ori	r5,r5,refresh_rates@l
-	lwzx	r5,r5,r3		/* get refresh rate in nSec */
-	divwu	r5,r5,r9		/* calculate # of SDC clocks */
-	stw	r5,SD_REFRESH(r4)	/* Set refresh rate */
-	sync
-
-	/* Program SD Timing Register */
-
-	li	r7, 0		/* clear r7 prior parameter collection */
-
-	READ_SPD(20)		/* get DIMM type: Registered or Unbuffered */
-	beq	spd_read_fail
-	li	r5, ERR_DIMM_TYPE
-	cmpi	0,0,r3,SPD_UDIMM
-	beq	do_cl
-	cmpi	0,0,r3,SPD_RDIMM
-	bne	spd_fail
-	oris	r7,r7,0x1000	/* set SD_TIMING[DIMM_TYPE] bit */
-
-do_cl:
-	READ_SPD(18)		/* Get CAS Latency */
-	beq	spd_read_fail
-	li	r5,ERR_CL_VALUE
-	andi.	r6,r3,SPD_CAS_3
-	beq	cl_4
-	li	r6,3
-	b	set_cl
-cl_4:
-	andi.	r6,r3,SPD_CAS_4
-	beq	cl_5
-	li	r6,4
-	b	set_cl
-cl_5:
-	andi.	r6,r3,SPD_CAS_5
-	beq	spd_fail
-	li	r6,5
-set_cl:
-	rlwimi	r7,r6,24,5,7
-
-	READ_SPD(30)		/* Get tRAS */
-	beq	spd_read_fail
-	divwu	r6,r3,r9
-	mullw	r8,r6,r9
-	subf.	r8,r8,r3
-	beq	set_tras
-	addi	r6,r6,1
-set_tras:
-	li r5,ERR_TRAS_FAIL
-	cmpi	0,0,r6,0x0F	/* max supported value */
-	bgt	spd_fail
-	rlwimi	r7,r6,16,12,15
-
-	READ_SPD(29)	/* Get tRCD */
-	beq	spd_read_fail
-	/* right shift tRCD by 2 bits as per DDR2 spec */
-	rlwinm	r3,r3,30,2,31
-	divwu	r6,r3,r9
-	mullw	r8,r6,r9
-	subf.	r8,r8,r3
-	beq	set_trcd
-	addi	r6,r6,1
-set_trcd:
-	li	r5,ERR_TRCD_FAIL
-	cmpi	0,0,r6,0x07	/* max supported value */
-	bgt	spd_fail
-	rlwimi	r7,r6,12,17,19
-
-	READ_SPD(27)	/* Get tRP value */
-	beq	spd_read_fail
-	rlwinm	r3,r3,30,2,31	/* right shift tRP by 2 bits as per DDR2 spec */
-	divwu	r6,r3,r9
-	mullw	r8,r6,r9
-	subf.	r8,r8,r3
-	beq	set_trp
-	addi	r6,r6,1
-set_trp:
-	li	r5,ERR_TRP_FAIL
-	cmpi	0,0,r6,0x07	/* max supported value */
-	bgt	spd_fail
-	rlwimi	r7,r6,8,21,23
-
-	READ_SPD(36)	/* Get tWR value */
-	beq	spd_read_fail
-	rlwinm	r3,r3,30,2,31	/* right shift tWR by 2 bits as per DDR2 spec */
-	divwu	r6,r3,r9
-	mullw	r8,r6,r9
-	subf.	r8,r8,r3
-	beq	set_twr
-	addi	r6,r6,1
-set_twr:
-	addi	r6,r6,-1	/* Tsi108 SDC always gives one extra clock */
-	li	r5,ERR_TWR_FAIL
-	cmpi	0,0,r6,0x07	/* max supported value */
-	bgt	spd_fail
-	rlwimi	r7,r6,5,24,26
-
-	READ_SPD(42)	/* Get tRFC */
-	beq	spd_read_fail
-	li	r5, ERR_TRFC_FAIL
-	/* Tsi108 spec: tRFC=(tRFC + 1)/2 */
-	addi	r3,r3,1
-	rlwinm.	r3,r3,31,1,31	/* divide by 2 */
-	beq	spd_fail
-	divwu	r6,r3,r9
-	mullw	r8,r6,r9
-	subf.	r8,r8,r3
-	beq	set_trfc
-	addi	r6,r6,1
-set_trfc:
-	cmpi	0,0,r6,0x1F	/* max supported value */
-	bgt	spd_fail
-	rlwimi	r7,r6,0,27,31
-
-	stw	r7,SD_TIMING(r4)
-	sync
-
-	/*
-	 * The following two registers are set on per-DIMM basis.
-	 * The SD_REFRESH and SD_TIMING settings are common for both DIMMS
-	 */
-
-do_each_dimm:
-
-	/* Program SDRAM DIMM Control Register */
-
-	li	r7, 0		/* clear r7 prior parameter collection */
-
-	READ_SPD(13)		/* Get Primary SDRAM Width */
-	beq	spd_read_fail
-	cmpi	0,0,r3,4	/* Check for 4-bit SDRAM */
-	beq	do_nbank
-	oris	r7,r7,0x0010	/* Set MEM_WIDTH bit */
-
-do_nbank:
-	READ_SPD(17)		/* Get Number of banks on SDRAM device */
-	beq	spd_read_fail
-	/* Grendel only distinguish betw. 4 or 8-bank memory parts */
-	li	r5,ERR_UNKNOWN_PART	/* non-supported memory part */
-	cmpi	0,0,r3,4
-	beq	do_nrank
-	cmpi	0,0,r3,8
-	bne	spd_fail
-	ori	r7,r7,0x1000
-
-do_nrank:
-	READ_SPD(5)		/* Get # of Ranks */
-	beq	spd_read_fail
-	li	r5,ERR_NRANK_INVALID
-	andi.	r6,r3,0x7	/* Use bits [2..0] only */
-	beq	do_addr_mode
-	cmpi	0,0,r6,1
-	bgt	spd_fail
-	rlwimi	r7,r6,8,23,23
-
-do_addr_mode:
-	READ_SPD(4)		/* Get # of Column Addresses */
-	beq	spd_read_fail
-	li	r5, ERR_ADDR_MODE
-	andi.	r3,r3,0x0f	/* cut off reserved bits */
-	cmpi	0,0,r3,8
-	ble	spd_fail
-	cmpi	0,0,r3,15
-	bgt	spd_fail
-	addi	r6,r3,-8	/* calculate ADDR_MODE parameter */
-	rlwimi	r7,r6,4,24,27	/* set ADDR_MODE field */
-
-set_dimm_ctrl:
-#ifdef SDC_AUTOPRECH_EN
-	oris	r7,r7,0x0001	/* set auto precharge EN bit */
-#endif
-	ori	r7,r7,1		/* set ENABLE bit */
-	cmpi	0,0,r10,SPD_DIMM0
-	bne	1f
-	stw	r7,SD_D0_CTRL(r4)
-	sync
-	b	set_dimm_bar
-1:
-	stw	r7,SD_D1_CTRL(r4)
-	sync
-
-
-	/* Program SDRAM DIMMx Base Address Register */
-
-set_dimm_bar:
-	READ_SPD(5)		/* get # of Ranks */
-	beq	spd_read_fail
-	andi.	r7,r3,0x7
-	addi	r7,r7,1
-	READ_SPD(31)		/* Read DIMM rank density */
-	beq	spd_read_fail
-	rlwinm	r5,r3,27,29,31
-	rlwinm	r6,r3,3,24,28
-	or	r5,r6,r5	/* r5 = Normalized Rank Density byte */
-	lis	r8, 0x0080	/* 128MB >> 4 */
-	mullw	r8,r8,r5	/* r8 = (rank_size >> 4) */
-	mullw	r8,r8,r7	/* r8 = (DIMM_size >> 4) */
-	neg	r7,r8
-	rlwinm	r7,r7,28,4,31
-	or	r7,r7,r11	/* set ADDR field */
-	rlwinm	r8,r8,12,20,31
-	add	r11,r11,r8	/* set Base Addr for next DIMM */
-
-	cmpi	0,0,r10,SPD_DIMM0
-	bne	set_dimm1_size
-	stw	r7,SD_D0_BAR(r4)
-	sync
-	li	r10,SPD_DIMM1
-	READ_SPD(0)
-	bne do_each_dimm
-	b spd_done
-
-set_dimm1_size:
-	stw	r7,SD_D1_BAR(r4)
-	sync
-spd_done:
-	blr
-
-check_next_slot:
-	cmpi	0,0,r10,SPD_DIMM1
-	beq	spd_read_fail
-	li	r10,SPD_DIMM1
-	b	do_first_dimm
-spd_read_fail:
-	ori	r3,r0,0xdead
-	b	err_hung
-spd_fail:
-	li	r3,0x0bad
-	sync
-err_hung:	/* hang here for debugging */
-	nop
-	nop
-	b	err_hung
-
-#endif /* !SDC_HARDCODED_INIT */
diff --git a/board/freescale/mpc7448hpc2/config.mk b/board/freescale/mpc7448hpc2/config.mk
deleted file mode 100644
index b2d6f76..0000000
--- a/board/freescale/mpc7448hpc2/config.mk
+++ /dev/null
@@ -1,7 +0,0 @@
-#
-# Copyright (c) 2005 Freescale Semiconductor, Inc.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-PLATFORM_CPPFLAGS += -maltivec -mabi=altivec -msoft-float
diff --git a/board/freescale/mpc7448hpc2/mpc7448hpc2.c b/board/freescale/mpc7448hpc2/mpc7448hpc2.c
deleted file mode 100644
index 11747ca..0000000
--- a/board/freescale/mpc7448hpc2/mpc7448hpc2.c
+++ /dev/null
@@ -1,89 +0,0 @@
-/*
- * (C) Copyright 2005 Freescale Semiconductor, Inc.
- *
- * Roy Zang <tie-fei.zang@freescale.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- *
- * modifications for the Tsi108 Emul Board by avb@Tundra
- */
-
-/*
- * board support/init functions for the
- * Freescale MPC7448 HPC2 (High-Performance Computing 2 Platform).
- */
-
-#include <common.h>
-#include <74xx_7xx.h>
-#include <fdt_support.h>
-#include <netdev.h>
-
-#undef	DEBUG
-
-DECLARE_GLOBAL_DATA_PTR;
-
-extern void tsi108_init_f (void);
-
-int display_mem_map (void);
-
-void after_reloc (ulong dest_addr)
-{
-	/*
-	 * Jump to the main U-Boot board init code
-	 */
-	board_init_r ((gd_t *) gd, dest_addr);
-	/* NOTREACHED */
-}
-
-/*
- * Check Board Identity:
- * report board type
- */
-
-int checkboard (void)
-{
-	int l_type = 0;
-
-	printf ("BOARD: %s\n", CONFIG_SYS_BOARD_NAME);
-	return (l_type);
-}
-
-/*
- * Read Processor ID:
- *
- * report calling processor number
- */
-
-int read_pid (void)
-{
-	return 0;		/* we are on single CPU platform for a while */
-}
-
-long int dram_size (int board_type)
-{
-	return 0x20000000;	/* 256M bytes */
-}
-
-phys_size_t initdram (int board_type)
-{
-	return dram_size (board_type);
-}
-
-#if defined(CONFIG_OF_BOARD_SETUP)
-int ft_board_setup(void *blob, bd_t *bd)
-{
-	ft_cpu_setup(blob, bd);
-	fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
-
-	return 0;
-}
-#endif
-
-int board_eth_init(bd_t *bis)
-{
-	int rc = 0;
-#if defined(CONFIG_TSI108_ETH)
-	rc = tsi108_eth_initialize(bis);
-#endif
-	return rc;
-}
diff --git a/board/freescale/mpc7448hpc2/tsi108_init.c b/board/freescale/mpc7448hpc2/tsi108_init.c
deleted file mode 100644
index 9a1e407..0000000
--- a/board/freescale/mpc7448hpc2/tsi108_init.c
+++ /dev/null
@@ -1,652 +0,0 @@
-/*****************************************************************************
- * (C) Copyright 2003;  Tundra Semiconductor Corp.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- *****************************************************************************/
-
-/*----------------------------------------------------------------------------
- * FILENAME: tsi108_init.c
- *
- * Originator: Alex Bounine
- *
- * DESCRIPTION:
- * Initialization code for the Tundra Tsi108 bridge chip
- *---------------------------------------------------------------------------*/
-
-#include <common.h>
-#include <74xx_7xx.h>
-#include <config.h>
-#include <version.h>
-#include <asm/processor.h>
-#include <tsi108.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-extern void mpicInit (int verbose);
-
-/*
- * Configuration Options
- */
-
-typedef struct {
-	ulong upper;
-	ulong lower;
-} PB2OCN_LUT_ENTRY;
-
-PB2OCN_LUT_ENTRY pb2ocn_lut1[32] = {
-	/* 0 - 7 */
-	{0x00000000, 0x00000201}, /* PBA=0xE000_0000 -> PCI/X (Byte-Swap) */
-	{0x00000000, 0x00000201}, /* PBA=0xE100_0000 -> PCI/X (Byte-Swap) */
-	{0x00000000, 0x00000201}, /* PBA=0xE200_0000 -> PCI/X (Byte-Swap) */
-	{0x00000000, 0x00000201}, /* PBA=0xE300_0000 -> PCI/X (Byte-Swap) */
-	{0x00000000, 0x00000201}, /* PBA=0xE400_0000 -> PCI/X (Byte-Swap) */
-	{0x00000000, 0x00000201}, /* PBA=0xE500_0000 -> PCI/X (Byte-Swap) */
-	{0x00000000, 0x00000201}, /* PBA=0xE600_0000 -> PCI/X (Byte-Swap) */
-	{0x00000000, 0x00000201}, /* PBA=0xE700_0000 -> PCI/X (Byte-Swap) */
-
-	/* 8 - 15 */
-	{0x00000000, 0x00000201}, /* PBA=0xE800_0000 -> PCI/X (Byte-Swap) */
-	{0x00000000, 0x00000201}, /* PBA=0xE900_0000 -> PCI/X (Byte-Swap) */
-	{0x00000000, 0x00000201}, /* PBA=0xEA00_0000 -> PCI/X (Byte-Swap) */
-	{0x00000000, 0x00000201}, /* PBA=0xEB00_0000 -> PCI/X (Byte-Swap) */
-	{0x00000000, 0x00000201}, /* PBA=0xEC00_0000 -> PCI/X (Byte-Swap) */
-	{0x00000000, 0x00000201}, /* PBA=0xED00_0000 -> PCI/X (Byte-Swap) */
-	{0x00000000, 0x00000201}, /* PBA=0xEE00_0000 -> PCI/X (Byte-Swap) */
-	{0x00000000, 0x00000201}, /* PBA=0xEF00_0000 -> PCI/X (Byte-Swap) */
-
-	/* 16 - 23 */
-	{0x00000000, 0x00000201}, /* PBA=0xF000_0000 -> PCI/X (Byte-Swap) */
-	{0x00000000, 0x00000201}, /* PBA=0xF100_0000 -> PCI/X (Byte-Swap) */
-	{0x00000000, 0x00000201}, /* PBA=0xF200_0000 -> PCI/X (Byte-Swap) */
-	{0x00000000, 0x00000201}, /* PBA=0xF300_0000 -> PCI/X (Byte-Swap) */
-	{0x00000000, 0x00000201}, /* PBA=0xF400_0000 -> PCI/X (Byte-Swap) */
-	{0x00000000, 0x00000201}, /* PBA=0xF500_0000 -> PCI/X (Byte-Swap) */
-	{0x00000000, 0x00000201}, /* PBA=0xF600_0000 -> PCI/X (Byte-Swap) */
-	{0x00000000, 0x00000201}, /* PBA=0xF700_0000 -> PCI/X (Byte-Swap) */
-	/* 24 - 31 */
-	{0x00000000, 0x00000201}, /* PBA=0xF800_0000 -> PCI/X (Byte-Swap) */
-	{0x00000000, 0x00000201}, /* PBA=0xF900_0000 -> PCI/X (Byte-Swap) */
-	{0x00000000, 0x00000241}, /* PBA=0xFA00_0000 -> PCI/X  PCI I/O (Byte-Swap + Translate) */
-	{0x00000000, 0x00000201}, /* PBA=0xFB00_0000 -> PCI/X  PCI Config (Byte-Swap) */
-
-	{0x00000000, 0x02000240}, /* PBA=0xFC00_0000 -> HLP */
-	{0x00000000, 0x01000240}, /* PBA=0xFD00_0000 -> HLP */
-	{0x00000000, 0x03000240}, /* PBA=0xFE00_0000 -> HLP */
-	{0x00000000, 0x00000240}  /* PBA=0xFF00_0000 -> HLP : (Translation Enabled + Byte-Swap)*/
-};
-
-#ifdef CONFIG_SYS_CLK_SPREAD
-typedef struct {
-	ulong ctrl0;
-	ulong ctrl1;
-} PLL_CTRL_SET;
-
-/*
- * Clock Generator SPLL0 initialization values
- * PLL0 configuration table for various PB_CLKO freq.
- * Uses pre-calculated values for Fs = 30 kHz, D = 0.5%
- * Fout depends on required PB_CLKO. Based on Fref = 33 MHz
- */
-
-static PLL_CTRL_SET pll0_config[8] = {
-	{0x00000000, 0x00000000},	/* 0: bypass */
-	{0x00000000, 0x00000000},	/* 1: reserved */
-	{0x00430044, 0x00000043},	/* 2: CG_PB_CLKO = 183 MHz */
-	{0x005c0044, 0x00000039},	/* 3: CG_PB_CLKO = 100 MHz */
-	{0x005c0044, 0x00000039},	/* 4: CG_PB_CLKO = 133 MHz */
-	{0x004a0044, 0x00000040},	/* 5: CG_PB_CLKO = 167 MHz */
-	{0x005c0044, 0x00000039},	/* 6: CG_PB_CLKO = 200 MHz */
-	{0x004f0044, 0x0000003e}	/* 7: CG_PB_CLKO = 233 MHz */
-};
-#endif	/* CONFIG_SYS_CLK_SPREAD */
-
-/*
- * Prosessor Bus Clock (in MHz) defined by CG_PB_SELECT
- * (based on recommended Tsi108 reference clock 33MHz)
- */
-static int pb_clk_sel[8] = { 0, 0, 183, 100, 133, 167, 200, 233 };
-
-/*
- * get_board_bus_clk ()
- *
- * returns the bus clock in Hz.
- */
-unsigned long get_board_bus_clk (void)
-{
-	ulong i;
-
-	/* Detect PB clock freq. */
-	i = in32(CONFIG_SYS_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PWRUP_STATUS);
-	i = (i >> 16) & 0x07;	/* Get PB PLL multiplier */
-
-	return pb_clk_sel[i] * 1000000;
-}
-
-/*
- * board_early_init_f ()
- *
- * board-specific initialization executed from flash
- */
-
-int board_early_init_f (void)
-{
-	ulong i;
-
-	gd->mem_clk = 0;
-	i = in32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET +
-			CG_PWRUP_STATUS);
-	i = (i >> 20) & 0x07;	/* Get GD PLL multiplier */
-	switch (i) {
-	case 0:	/* external clock */
-		printf ("Using external clock\n");
-		break;
-	case 1:	/* system clock */
-		gd->mem_clk = gd->bus_clk;
-		break;
-	case 4:	/* 133 MHz */
-	case 5:	/* 166 MHz */
-	case 6:	/* 200 MHz */
-		gd->mem_clk = pb_clk_sel[i] * 1000000;
-		break;
-	default:
-		printf ("Invalid DDR2 clock setting\n");
-		return -1;
-	}
-	printf ("BUS: %lu MHz\n", get_board_bus_clk() / 1000000);
-	printf ("MEM: %lu MHz\n", gd->mem_clk / 1000000);
-	return 0;
-}
-
-/*
- * board_early_init_r() - Tsi108 initialization function executed right after
- * relocation. Contains code that cannot be executed from flash.
- */
-
-int board_early_init_r (void)
-{
-	ulong temp, i;
-	ulong reg_val;
-	volatile ulong *reg_ptr;
-
-	reg_ptr =
-		(ulong *) (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + 0x900);
-
-	for (i = 0; i < 32; i++) {
-		*reg_ptr++ = 0x00000201;	/* SWAP ENABLED */
-		*reg_ptr++ = 0x00;
-	}
-
-	__asm__ __volatile__ ("eieio");
-	__asm__ __volatile__ ("sync");
-
-	/* Setup PB_OCN_BAR2: size 256B + ENable @ 0x0_80000000 */
-
-	out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_OCN_BAR2,
-		0x80000001);
-	__asm__ __volatile__ ("sync");
-
-	/* Make sure that OCN_BAR2 decoder is set (to allow following immediate
-	 * read from SDRAM)
-	 */
-
-	temp = in32(CONFIG_SYS_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_OCN_BAR2);
-	__asm__ __volatile__ ("sync");
-
-	/*
-	 * Remap PB_OCN_BAR1 to accomodate PCI-bus aperture and EPROM into the
-	 * processor bus address space. Immediately after reset LUT and address
-	 * translation are disabled for this BAR. Now we have to initialize LUT
-	 * and switch from the BOOT mode to the normal operation mode.
-	 *
-	 * The aperture defined by PB_OCN_BAR1 startes at address 0xE0000000
-	 * and covers 512MB of address space. To allow larger aperture we also
-	 * have to relocate register window of Tsi108
-	 *
-	 * Initialize LUT (32-entries) prior switching PB_OCN_BAR1 from BOOT
-	 * mode.
-	 *
-	 * initialize pointer to LUT associated with PB_OCN_BAR1
-	 */
-	reg_ptr =
-		(ulong *) (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + 0x800);
-
-	for (i = 0; i < 32; i++) {
-		*reg_ptr++ = pb2ocn_lut1[i].lower;
-		*reg_ptr++ = pb2ocn_lut1[i].upper;
-	}
-
-	__asm__ __volatile__ ("sync");
-
-	/* Base addresses for CS0, CS1, CS2, CS3 */
-
-	out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B0_ADDR,
-		0x00000000);
-	__asm__ __volatile__ ("sync");
-
-	out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B1_ADDR,
-		0x00100000);
-	__asm__ __volatile__ ("sync");
-
-	out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B2_ADDR,
-		0x00200000);
-	__asm__ __volatile__ ("sync");
-
-	out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B3_ADDR,
-		0x00300000);
-	__asm__ __volatile__ ("sync");
-
-	/* Masks for HLP banks */
-
-	out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B0_MASK,
-		0xFFF00000);
-	__asm__ __volatile__ ("sync");
-
-	out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B1_MASK,
-		0xFFF00000);
-	__asm__ __volatile__ ("sync");
-
-	out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B2_MASK,
-		0xFFF00000);
-	__asm__ __volatile__ ("sync");
-
-	out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B3_MASK,
-		0xFFF00000);
-	__asm__ __volatile__ ("sync");
-
-	/* Set CTRL0 values for banks */
-
-	out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B0_CTRL0,
-		0x7FFC44C2);
-	__asm__ __volatile__ ("sync");
-
-	out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B1_CTRL0,
-		0x7FFC44C0);
-	__asm__ __volatile__ ("sync");
-
-	out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B2_CTRL0,
-		0x7FFC44C0);
-	__asm__ __volatile__ ("sync");
-
-	out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B3_CTRL0,
-		0x7FFC44C2);
-	__asm__ __volatile__ ("sync");
-
-	/* Set banks to latched mode, enabled, and other default settings */
-
-	out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B0_CTRL1,
-		0x7C0F2000);
-	__asm__ __volatile__ ("sync");
-
-	out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B1_CTRL1,
-		0x7C0F2000);
-	__asm__ __volatile__ ("sync");
-
-	out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B2_CTRL1,
-		0x7C0F2000);
-	__asm__ __volatile__ ("sync");
-
-	out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B3_CTRL1,
-		0x7C0F2000);
-	__asm__ __volatile__ ("sync");
-
-	/*
-	 * Set new value for PB_OCN_BAR1: switch from BOOT to LUT mode.
-	 * value for PB_OCN_BAR1: (BA-0xE000_0000 + size 512MB + ENable)
-	 */
-	out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_OCN_BAR1,
-		0xE0000011);
-	__asm__ __volatile__ ("sync");
-
-	/* Make sure that OCN_BAR2 decoder is set (to allow following
-	 * immediate read from SDRAM)
-	 */
-
-	temp = in32(CONFIG_SYS_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_OCN_BAR1);
-	__asm__ __volatile__ ("sync");
-
-	/*
-	 * SRI: At this point we have enabled the HLP banks. That means we can
-	 * now read from the NVRAM and initialize the environment variables.
-	 * We will over-ride the env_init called in board_init_f
-	 * This is really a work-around because, the HLP bank 1
-	 * where NVRAM resides is not visible during board_init_f
-	 * (arch/powerpc/lib/board.c)
-	 * Alternatively, we could use the I2C EEPROM at start-up to configure
-	 * and enable all HLP banks and not just HLP 0 as is being done for
-	 * Taiga Rev. 2.
-	 */
-
-	env_init ();
-
-#ifndef DISABLE_PBM
-
-	/*
-	 * For IBM processors we have to set Address-Only commands generated
-	 * by PBM that are different from ones set after reset.
-	 */
-
-	temp = get_cpu_type ();
-
-	if ((CPU_750FX == temp) || (CPU_750GX == temp))
-		out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_MCMD,
-			0x00009955);
-#endif	/* DISABLE_PBM */
-
-#ifdef CONFIG_PCI
-	/*
-	 * Initialize PCI/X block
-	 */
-
-	/* Map PCI/X Configuration Space (16MB @ 0x0_FE000000) */
-	out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET +
-		PCI_PFAB_BAR0_UPPER, 0);
-	__asm__ __volatile__ ("sync");
-
-	out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_PFAB_BAR0,
-		0xFB000001);
-	__asm__ __volatile__ ("sync");
-
-	/* Set Bus Number for the attached PCI/X bus (we will use 0 for NB) */
-
-	temp =	in32(CONFIG_SYS_TSI108_CSR_BASE +
-		TSI108_PCI_REG_OFFSET + PCI_PCIX_STAT);
-
-	temp &= ~0xFF00;	/* Clear the BUS_NUM field */
-
-	out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_PCIX_STAT,
-		temp);
-
-	/* Map PCI/X IO Space (64KB @ 0x0_FD000000) takes one 16MB LUT entry */
-
-	out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_PFAB_IO_UPPER,
-		0);
-	__asm__ __volatile__ ("sync");
-
-	/* This register is on the PCI side to interpret the address it receives
-	 * and maps it as a IO address.
-	 */
-
-	out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_PFAB_IO,
-		0x00000001);
-	__asm__ __volatile__ ("sync");
-
-	/*
-	 * Map PCI/X Memory Space
-	 *
-	 * Transactions directed from OCM to PCI Memory Space are directed
-	 * from PB to PCI
-	 * unchanged (as defined by PB_OCN_BAR1,2 and LUT settings).
-	 * If address remapping is required the corresponding PCI_PFAB_MEM32
-	 * and PCI_PFAB_PFMx register groups have to be configured.
-	 *
-	 * Map the path from the PCI/X bus into the system memory
-	 *
-	 * The memory mapped window assotiated with PCI P2O_BAR2 provides
-	 * access to the system memory without address remapping.
-	 * All system memory is opened for accesses initiated by PCI/X bus
-	 * masters.
-	 *
-	 * Initialize LUT associated with PCI P2O_BAR2
-	 *
-	 * set pointer to LUT associated with PCI P2O_BAR2
-	 */
-
-	reg_ptr =
-		(ulong *) (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + 0x500);
-
-#ifdef DISABLE_PBM
-
-	/* In case when PBM is disabled (no HW supported cache snoopng on PB)
-	 * P2O_BAR2 is directly mapped into the system memory without address
-	 * translation.
-	 */
-
-	reg_val = 0x00000004;	/* SDRAM port + NO Addr_Translation */
-
-	for (i = 0; i < 32; i++) {
-		*reg_ptr++ = reg_val;	/* P2O_BAR2_LUTx */
-		*reg_ptr++ = 0;		/* P2O_BAR2_LUT_UPPERx */
-	}
-
-	/* value for PCI BAR2 (size = 512MB, Enabled, No Addr. Translation) */
-	reg_val = 0x00007500;
-#else
-
-	reg_val = 0x00000002;	/* Destination port = PBM */
-
-	for (i = 0; i < 32; i++) {
-		*reg_ptr++ = reg_val;	/* P2O_BAR2_LUTx */
-/* P2O_BAR2_LUT_UPPERx : Set data swapping mode for PBM (byte swapping) */
-		*reg_ptr++ = 0x40000000;
-/* offset = 16MB, address translation is enabled to allow byte swapping */
-		reg_val += 0x01000000;
-	}
-
-/* value for PCI BAR2 (size = 512MB, Enabled, Address Translation Enabled) */
-	reg_val = 0x00007100;
-#endif
-
-	__asm__ __volatile__ ("eieio");
-	__asm__ __volatile__ ("sync");
-
-	out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_PAGE_SIZES,
-		reg_val);
-	__asm__ __volatile__ ("sync");
-
-	/* Set 64-bit PCI bus address for system memory
-	 * ( 0 is the best choice for easy mapping)
-	 */
-
-	out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR2,
-		0x00000000);
-	out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR2_UPPER,
-		0x00000000);
-	__asm__ __volatile__ ("sync");
-
-#ifndef DISABLE_PBM
-	/*
-	 *  The memory mapped window assotiated with PCI P2O_BAR3 provides
-	 *  access to the system memory using SDRAM OCN port and address
-	 *  translation. This is alternative way to access SDRAM from PCI
-	 *  required for Tsi108 emulation testing.
-	 *  All system memory is opened for accesses initiated by
-	 *  PCI/X bus masters.
-	 *
-	 *  Initialize LUT associated with PCI P2O_BAR3
-	 *
-	 *  set pointer to LUT associated with PCI P2O_BAR3
-	 */
-	reg_ptr =
-		(ulong *) (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + 0x600);
-
-	reg_val = 0x00000004;	/* Destination port = SDC */
-
-	for (i = 0; i < 32; i++) {
-		*reg_ptr++ = reg_val;	/* P2O_BAR3_LUTx */
-
-/* P2O_BAR3_LUT_UPPERx : Set data swapping mode for PBM (byte swapping) */
-		*reg_ptr++ = 0;
-
-/* offset = 16MB, address translation is enabled to allow byte swapping */
-		reg_val += 0x01000000;
-	}
-
-	__asm__ __volatile__ ("eieio");
-	__asm__ __volatile__ ("sync");
-
-	/* Configure PCI P2O_BAR3 (size = 512MB, Enabled) */
-
-	reg_val =
-		in32(CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET +
-		 PCI_P2O_PAGE_SIZES);
-	reg_val &= ~0x00FF;
-	reg_val |= 0x0071;
-	out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_PAGE_SIZES,
-		reg_val);
-	__asm__ __volatile__ ("sync");
-
-	/* Set 64-bit base PCI bus address for window (0x20000000) */
-
-	out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR3_UPPER,
-		0x00000000);
-	out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR3,
-		0x20000000);
-	__asm__ __volatile__ ("sync");
-
-#endif	/* !DISABLE_PBM */
-
-#ifdef ENABLE_PCI_CSR_BAR
-	/* open if required access to Tsi108 CSRs from the PCI/X bus */
-	/* enable BAR0 on the PCI/X bus */
-	reg_val = in32(CONFIG_SYS_TSI108_CSR_BASE +
-		TSI108_PCI_REG_OFFSET + PCI_MISC_CSR);
-	reg_val |= 0x02;
-	out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_MISC_CSR,
-		reg_val);
-	__asm__ __volatile__ ("sync");
-
-	out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR0_UPPER,
-		0x00000000);
-	out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR0,
-		CONFIG_SYS_TSI108_CSR_BASE);
-	__asm__ __volatile__ ("sync");
-
-#endif
-
-	/*
-	 * Finally enable PCI/X Bus Master and Memory Space access
-	 */
-
-	reg_val = in32(CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_CSR);
-	reg_val |= 0x06;
-	out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_CSR, reg_val);
-	__asm__ __volatile__ ("sync");
-
-#endif	/* CONFIG_PCI */
-
-	/*
-	 * Initialize MPIC outputs (interrupt pins):
-	 * Interrupt routing on the Grendel Emul. Board:
-	 * PB_INT[0] -> INT (CPU0)
-	 * PB_INT[1] -> INT (CPU1)
-	 * PB_INT[2] -> MCP (CPU0)
-	 * PB_INT[3] -> MCP (CPU1)
-	 * Set interrupt controller outputs as Level_Sensitive/Active_Low
-	 */
-	out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_MPIC_REG_OFFSET + MPIC_CSR(0), 0x02);
-	out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_MPIC_REG_OFFSET + MPIC_CSR(1), 0x02);
-	out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_MPIC_REG_OFFSET + MPIC_CSR(2), 0x02);
-	out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_MPIC_REG_OFFSET + MPIC_CSR(3), 0x02);
-	__asm__ __volatile__ ("sync");
-
-	/*
-	 * Ensure that Machine Check exception is enabled
-	 * We need it to support PCI Bus probing (configuration reads)
-	 */
-
-	reg_val = mfmsr ();
-	mtmsr(reg_val | MSR_ME);
-
-	return 0;
-}
-
-/*
- * Needed to print out L2 cache info
- * used in the misc_init_r function
- */
-
-unsigned long get_l2cr (void)
-{
-	unsigned long l2controlreg;
-	asm volatile ("mfspr %0, 1017":"=r" (l2controlreg):);
-	return l2controlreg;
-}
-
-/*
- * misc_init_r()
- *
- * various things to do after relocation
- *
- */
-
-int misc_init_r (void)
-{
-#ifdef CONFIG_SYS_CLK_SPREAD	/* Initialize Spread-Spectrum Clock generation */
-	ulong i;
-
-	/* Ensure that Spread-Spectrum is disabled */
-	out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL0_CTRL0, 0);
-	out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL1_CTRL0, 0);
-
-	/* Initialize PLL1: CG_PCI_CLK , internal OCN_CLK
-	 * Uses pre-calculated value for Fout = 800 MHz, Fs = 30 kHz, D = 0.5%
-	 */
-
-	out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL1_CTRL0,
-		0x002e0044);	/* D = 0.25% */
-	out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL1_CTRL1,
-		0x00000039);	/* BWADJ */
-
-	/* Initialize PLL0: CG_PB_CLKO  */
-	/* Detect PB clock freq. */
-	i = in32(CONFIG_SYS_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PWRUP_STATUS);
-	i = (i >> 16) & 0x07;	/* Get PB PLL multiplier */
-
-	out32 (CONFIG_SYS_TSI108_CSR_BASE +
-		TSI108_CLK_REG_OFFSET + CG_PLL0_CTRL0, pll0_config[i].ctrl0);
-	out32 (CONFIG_SYS_TSI108_CSR_BASE +
-		TSI108_CLK_REG_OFFSET + CG_PLL0_CTRL1, pll0_config[i].ctrl1);
-
-	/* Wait and set SSEN for both PLL0 and 1 */
-	udelay (1000);
-	out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL1_CTRL0,
-		0x802e0044);	/* D=0.25% */
-	out32 (CONFIG_SYS_TSI108_CSR_BASE +
-		TSI108_CLK_REG_OFFSET + CG_PLL0_CTRL0,
-		0x80000000 | pll0_config[i].ctrl0);
-#endif	/* CONFIG_SYS_CLK_SPREAD */
-
-#ifdef CONFIG_SYS_L2
-	l2cache_enable ();
-#endif
-	printf ("BUS:   %lu MHz\n", gd->bus_clk / 1000000);
-	printf ("MEM:   %lu MHz\n", gd->mem_clk / 1000000);
-
-	/*
-	 * All the information needed to print the cache details is avaiblable
-	 * at this point i.e. above call to l2cache_enable is the very last
-	 * thing done with regards to enabling diabling the cache.
-	 * So this seems like a good place to print all this information
-	 */
-
-	printf ("CACHE: ");
-	switch (get_cpu_type()) {
-	case CPU_7447A:
-		printf ("L1 Instruction cache - 32KB 8-way");
-		(get_hid0 () & (1 << 15)) ? printf (" ENABLED\n") :
-			printf (" DISABLED\n");
-		printf ("L1 Data cache - 32KB 8-way");
-		(get_hid0 () & (1 << 14)) ? printf (" ENABLED\n") :
-			printf (" DISABLED\n");
-		printf ("Unified L2 cache - 512KB 8-way");
-		(get_l2cr () & (1 << 31)) ? printf (" ENABLED\n") :
-			printf (" DISABLED\n");
-		printf ("\n");
-		break;
-
-	case CPU_7448:
-		printf ("L1 Instruction cache - 32KB 8-way");
-		(get_hid0 () & (1 << 15)) ? printf (" ENABLED\n") :
-			printf (" DISABLED\n");
-		printf ("L1 Data cache - 32KB 8-way");
-		(get_hid0 () & (1 << 14)) ? printf (" ENABLED\n") :
-			printf (" DISABLED\n");
-		printf ("Unified L2 cache - 1MB 8-way");
-		(get_l2cr () & (1 << 31)) ? printf (" ENABLED\n") :
-			printf (" DISABLED\n");
-		break;
-	default:
-		break;
-	}
-	return 0;
-}