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| author | York Sun <york.sun@nxp.com> | 2016-05-26 13:59:03 -0700 |
|---|---|---|
| committer | York Sun <york.sun@nxp.com> | 2016-06-03 14:12:48 -0700 |
| commit | 931e8751af8ca9ff4395c3f033c5217d48f5698f (patch) | |
| tree | 7859b6b72bbe40cc58ca4cc63ac42594281d2f62 /board/freescale | |
| parent | 3378727d13dac410d8ef2d8426d4c9bfc4974405 (diff) | |
| download | u-boot-imx-931e8751af8ca9ff4395c3f033c5217d48f5698f.zip u-boot-imx-931e8751af8ca9ff4395c3f033c5217d48f5698f.tar.gz u-boot-imx-931e8751af8ca9ff4395c3f033c5217d48f5698f.tar.bz2 | |
board: ls2080ardb: qds: Fix compiling issue when FSL_MC_ENET not defined
U-Boot should continue to work without management complex (MC).
Fix compiling errors and warnings.
Signed-off-by: York Sun <york.sun@nxp.com>
Diffstat (limited to 'board/freescale')
| -rw-r--r-- | board/freescale/ls2080aqds/ls2080aqds.c | 2 | ||||
| -rw-r--r-- | board/freescale/ls2080ardb/ls2080ardb.c | 6 |
2 files changed, 8 insertions, 0 deletions
diff --git a/board/freescale/ls2080aqds/ls2080aqds.c b/board/freescale/ls2080aqds/ls2080aqds.c index b3bd40a..897793d 100644 --- a/board/freescale/ls2080aqds/ls2080aqds.c +++ b/board/freescale/ls2080aqds/ls2080aqds.c @@ -282,7 +282,9 @@ void fdt_fixup_board_enet(void *fdt) #ifdef CONFIG_OF_BOARD_SETUP int ft_board_setup(void *blob, bd_t *bd) { +#ifdef CONFIG_FSL_MC_ENET int err; +#endif u64 base[CONFIG_NR_DRAM_BANKS]; u64 size[CONFIG_NR_DRAM_BANKS]; diff --git a/board/freescale/ls2080ardb/ls2080ardb.c b/board/freescale/ls2080ardb/ls2080ardb.c index fb39af6..52e5e3f 100644 --- a/board/freescale/ls2080ardb/ls2080ardb.c +++ b/board/freescale/ls2080ardb/ls2080ardb.c @@ -156,7 +156,9 @@ int board_init(void) { char *env_hwconfig; u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE; +#ifdef CONFIG_FSL_MC_ENET u32 __iomem *irq_ccsr = (u32 __iomem *)ISC_BASE; +#endif u32 val; init_final_memctl_regs(); @@ -178,8 +180,10 @@ int board_init(void) QIXIS_WRITE(rst_ctl, QIXIS_RST_CTL_RESET_EN); +#ifdef CONFIG_FSL_MC_ENET /* invert AQR405 IRQ pins polarity */ out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR405_IRQ_MASK); +#endif return 0; } @@ -261,7 +265,9 @@ void fdt_fixup_board_enet(void *fdt) #ifdef CONFIG_OF_BOARD_SETUP int ft_board_setup(void *blob, bd_t *bd) { +#ifdef CONFIG_FSL_MC_ENET int err; +#endif u64 base[CONFIG_NR_DRAM_BANKS]; u64 size[CONFIG_NR_DRAM_BANKS]; |