diff options
| author | Prabhakar Kushwaha <prabhakar@freescale.com> | 2014-10-29 22:33:55 +0530 |
|---|---|---|
| committer | York Sun <yorksun@freescale.com> | 2014-12-05 08:06:09 -0800 |
| commit | 31530e0b8a411398efde40edbec12a7cf262926e (patch) | |
| tree | c45b836c08a2d57e0755f454eac2c4beef2b07a3 /board/freescale | |
| parent | 9f074e67f5a2131336ff1838f2a82e0c2e15d33c (diff) | |
| download | u-boot-imx-31530e0b8a411398efde40edbec12a7cf262926e.zip u-boot-imx-31530e0b8a411398efde40edbec12a7cf262926e.tar.gz u-boot-imx-31530e0b8a411398efde40edbec12a7cf262926e.tar.bz2 | |
board/t104xrdb: Conditional workaround of errata A-008044
Workaround of Errata A-008044 was implemented without errata number and it is
enabled by default. Errata A-008044 is only valid for T1040 Rev 1.0.
So put errata number and make it conditional.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'board/freescale')
| -rw-r--r-- | board/freescale/t104xrdb/spl.c | 22 |
1 files changed, 14 insertions, 8 deletions
diff --git a/board/freescale/t104xrdb/spl.c b/board/freescale/t104xrdb/spl.c index 75d9d9c..e394b12 100644 --- a/board/freescale/t104xrdb/spl.c +++ b/board/freescale/t104xrdb/spl.c @@ -36,18 +36,24 @@ void board_init_f(ulong bootflag) u32 plat_ratio, sys_clk, uart_clk; #if defined(CONFIG_SPL_NAND_BOOT) && defined(CONFIG_A008044_WORKAROUND) u32 porsr1, pinctl; + u32 svr = get_svr(); #endif ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; #if defined(CONFIG_SPL_NAND_BOOT) && defined(CONFIG_A008044_WORKAROUND) - /* - * There is T1040 SoC issue where NOR, FPGA are inaccessible during - * NAND boot because IFC signals > IFC_AD7 are not enabled. - * This workaround changes RCW source to make all signals enabled. - */ - porsr1 = in_be32(&gur->porsr1); - pinctl = ((porsr1 & ~(FSL_CORENET_CCSR_PORSR1_RCW_MASK)) | 0x24800000); - out_be32((unsigned int *)(CONFIG_SYS_DCSRBAR + 0x20000), pinctl); + if (IS_SVR_REV(svr, 1, 0)) { + /* + * There is T1040 SoC issue where NOR, FPGA are inaccessible + * during NAND boot because IFC signals > IFC_AD7 are not + * enabled. This workaround changes RCW source to make all + * signals enabled. + */ + porsr1 = in_be32(&gur->porsr1); + pinctl = ((porsr1 & ~(FSL_CORENET_CCSR_PORSR1_RCW_MASK)) + | 0x24800000); + out_be32((unsigned int *)(CONFIG_SYS_DCSRBAR + 0x20000), + pinctl); + } #endif /* Memcpy existing GD at CONFIG_SPL_GD_ADDR */ |