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| author | Marc Zyngier <marc.zyngier@arm.com> | 2014-07-12 14:24:08 +0100 |
|---|---|---|
| committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2014-07-28 17:19:55 +0200 |
| commit | 9d195a546179bc732aba9eacccf0a9a3db591288 (patch) | |
| tree | 3a133a6d6ad4afbd05ffcb6ba9e136a9ff5054c7 /board/freescale | |
| parent | e771a3d538a4fbe235864061ff3c81a8acb11082 (diff) | |
| download | u-boot-imx-9d195a546179bc732aba9eacccf0a9a3db591288.zip u-boot-imx-9d195a546179bc732aba9eacccf0a9a3db591288.tar.gz u-boot-imx-9d195a546179bc732aba9eacccf0a9a3db591288.tar.bz2 | |
ARM: HYP/non-sec: remove MIDR check to validate CBAR
Having a form of whitelist to check if we know of a CPU core
and and obtain CBAR is a bit silly.
It doesn't scale (how about A12, A17, as well as other I don't know
about?), and is actually a property of the SoC, not the core.
So either it works and everybody is happy, or it doesn't and
the u-boot port to this SoC is providing the real address via
a configuration option.
The result of the above is that this code doesn't need to exist,
is thus forcefully removed.
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Diffstat (limited to 'board/freescale')
0 files changed, 0 insertions, 0 deletions