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| author | Poonam Aggrwal <poonam.aggrwal@freescale.com> | 2011-02-09 20:05:29 +0000 |
|---|---|---|
| committer | Kumar Gala <galak@kernel.crashing.org> | 2011-04-04 09:24:42 -0500 |
| commit | e0082f7cb4985b7fbf3a69fbf884a85bd15af87a (patch) | |
| tree | da6abe2cfff5cea9cbed2d11f39c12d1f00b00be /board/freescale | |
| parent | 66c74fca18aab4c4182be486641d7a374689c4c3 (diff) | |
| download | u-boot-imx-e0082f7cb4985b7fbf3a69fbf884a85bd15af87a.zip u-boot-imx-e0082f7cb4985b7fbf3a69fbf884a85bd15af87a.tar.gz u-boot-imx-e0082f7cb4985b7fbf3a69fbf884a85bd15af87a.tar.bz2 | |
powerpc/85xx: Add 36-bit physical addressing support for P1_P2_RDB
Add support for 36-bit address map for NOR, SD, and SPI boot cfgs.
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Priyanka Jain <priyanka.jain@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'board/freescale')
| -rw-r--r-- | board/freescale/p1_p2_rdb/p1_p2_rdb.c | 3 | ||||
| -rw-r--r-- | board/freescale/p1_p2_rdb/tlb.c | 9 |
2 files changed, 8 insertions, 4 deletions
diff --git a/board/freescale/p1_p2_rdb/p1_p2_rdb.c b/board/freescale/p1_p2_rdb/p1_p2_rdb.c index d4b4b68..307c3e2 100644 --- a/board/freescale/p1_p2_rdb/p1_p2_rdb.c +++ b/board/freescale/p1_p2_rdb/p1_p2_rdb.c @@ -107,6 +107,9 @@ int checkboard (void) cpu = gd->cpu; printf ("Board: %sRDB Rev%c\n", cpu->name, board_rev); +#ifdef CONFIG_PHYS_64BIT + puts ("(36-bit addrmap) \n"); +#endif setbits_be32(&pgpio->gpdir, GPIO_DIR); /* diff --git a/board/freescale/p1_p2_rdb/tlb.c b/board/freescale/p1_p2_rdb/tlb.c index 9b166b2..1847935 100644 --- a/board/freescale/p1_p2_rdb/tlb.c +++ b/board/freescale/p1_p2_rdb/tlb.c @@ -25,19 +25,20 @@ struct fsl_e_tlb_entry tlb_table[] = { /* TLB 0 - for temp stack in cache */ - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, + CONFIG_SYS_INIT_RAM_ADDR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , - CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , - CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , - CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), |