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authorNitin Garg <nitin.garg@freescale.com>2014-05-27 18:09:27 -0500
committerNitin Garg <nitin.garg@freescale.com>2014-06-13 10:17:01 -0500
commitd63fc607061d8b6f0d60055f1d38dae346d93024 (patch)
tree60f8cb3cba52078898a314fbe0da82c98f13f6d1 /board/freescale
parentcaf940dcc880b777365e35294ab757609fc9ac5a (diff)
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ENGR00315499-12: ARM: MSL: add i2c0 support for imx6sl evk
- Add i2c0 support for imx6sl evk platform. - Read pmic device ID and revsion ID. Signed-off-by: Fugang Duan <B38611@freescale.com> Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
Diffstat (limited to 'board/freescale')
-rw-r--r--board/freescale/mx6slevk/mx6slevk.c101
1 files changed, 101 insertions, 0 deletions
diff --git a/board/freescale/mx6slevk/mx6slevk.c b/board/freescale/mx6slevk/mx6slevk.c
index 7ddd553..ac0b1f3 100644
--- a/board/freescale/mx6slevk/mx6slevk.c
+++ b/board/freescale/mx6slevk/mx6slevk.c
@@ -42,11 +42,33 @@ DECLARE_GLOBAL_DATA_PTR;
PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
+ PAD_CTL_ODE | PAD_CTL_SRE_FAST)
+
#define EPDC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_SPEED_MED | \
PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
#define ETH_PHY_RESET IMX_GPIO_NR(4, 21)
+#ifdef CONFIG_SYS_I2C_MXC
+#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
+/* I2C1 for PMIC */
+struct i2c_pads_info i2c_pad_info0 = {
+ .scl = {
+ .i2c_mode = MX6_PAD_I2C1_SDA__I2C1_SDA | PC,
+ .gpio_mode = MX6_PAD_I2C1_SDA__GPIO_3_13 | PC,
+ .gp = IMX_GPIO_NR(3, 13),
+ },
+ .sda = {
+ .i2c_mode = MX6_PAD_I2C1_SCL__I2C1_SCL | PC,
+ .gpio_mode = MX6_PAD_I2C1_SCL__GPIO_3_12 | PC,
+ .gp = IMX_GPIO_NR(3, 12),
+ },
+};
+#endif
+
int dram_init(void)
{
gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
@@ -563,6 +585,75 @@ static int setup_fec(void)
}
#endif
+#ifdef CONFIG_SYS_I2C_MXC
+static int setup_pmic_voltages(void)
+{
+ unsigned char value, rev_id = 0;
+
+ i2c_set_bus_num(0);
+ if (!i2c_probe(0x8)) {
+ if (i2c_read(0x8, 0, 1, &value, 1)) {
+ printf("Read device ID error!\n");
+ return -1;
+ }
+ if (i2c_read(0x8, 3, 1, &rev_id, 1)) {
+ printf("Read Rev ID error!\n");
+ return -1;
+ }
+ printf("Found PFUZE100! deviceid=%x,revid=%x\n", value, rev_id);
+
+ /* set SW1AB staby volatage 0.975V */
+ if (i2c_read(0x8, 0x21, 1, &value, 1)) {
+ printf("Read SW1ABSTBY error!\n");
+ return -1;
+ }
+ value &= ~0x3f;
+ value |= 0x1b;
+ if (i2c_write(0x8, 0x21, 1, &value, 1)) {
+ printf("Set SW1ABSTBY error!\n");
+ return -1;
+ }
+
+ /* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
+ if (i2c_read(0x8, 0x24, 1, &value, 1)) {
+ printf("Read SW1ABCONFIG error!\n");
+ return -1;
+ }
+ value &= ~0xc0;
+ value |= 0x40;
+ if (i2c_write(0x8, 0x24, 1, &value, 1)) {
+ printf("Set SW1ABCONFIG error!\n");
+ return -1;
+ }
+
+ /* set SW1C staby volatage 0.975V */
+ if (i2c_read(0x8, 0x2f, 1, &value, 1)) {
+ printf("Read SW1CSTBY error!\n");
+ return -1;
+ }
+ value &= ~0x3f;
+ value |= 0x1b;
+ if (i2c_write(0x8, 0x2f, 1, &value, 1)) {
+ printf("Set SW1CSTBY error!\n");
+ return -1;
+ }
+
+ /* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */
+ if (i2c_read(0x8, 0x32, 1, &value, 1)) {
+ printf("Read SW1CCONFIG error!\n");
+ return -1;
+ }
+ value &= ~0xc0;
+ value |= 0x40;
+ if (i2c_write(0x8, 0x32, 1, &value, 1)) {
+ printf("Set SW1CCONFIG error!\n");
+ return -1;
+ }
+ }
+
+ return 0;
+}
+
#ifdef CONFIG_LDO_BYPASS_CHECK
void ldo_mode_set(int ldo_bypass)
{
@@ -598,6 +689,7 @@ void ldo_mode_set(int ldo_bypass)
}
#endif
+#endif
int board_early_init_f(void)
{
@@ -622,6 +714,15 @@ int board_init(void)
int board_late_init(void)
{
+ int ret = 0;
+
+#ifdef CONFIG_SYS_I2C_MXC
+ setup_i2c(0, CONFIG_SYS_I2C_SPEED,
+ CONFIG_SYS_I2C_SLAVE, &i2c_pad_info0);
+ ret = setup_pmic_voltages();
+ if (ret)
+ return -1;
+#endif
#ifdef CONFIG_ENV_IS_IN_MMC
board_late_mmc_env_init();