ENGR00169919 MX6Q ARM2 U-Boot : Support Pop CPU Board

Add support for MX6Q ARM2 LPDDR2 POP CPU Board. Change thing include
- TEXT_BASE
- RAM address and size
- Initialization DCD
- MMU related code

Use mx6q_arm2_lpddr2pop_config as the build config. After u-boot.bin is
generated, set the board to serial download mode, use sb loader to run the
bootloader.

There is one line in the original DDR initialization script
setmem /32 0x00B00000 = 0x1
however this address can not be accessed by DCD. A try to add it later in
"dram_init" block the boot up. Waiting for IC team to give an explanation
on it. Hold temperorily

The MMU Change can be concluded as the following
 - Cacheable and Uncacheable SDRAM allocation changes to
	Phys		Virtual		Size		Property
	----------	----------	--------	----------
	0x10000000	0x10000000	256M		cacheable
	0x80000000	0x20000000	16M		uncacheable
	0x81000000	0x21000000	240M		cacheable

 - TEXT_BASE change to 0x10800000, which reserves 8MB of memory at the start
   of SDRAM. This address makes sure that the text section of U-boot have the
   same Physical and Virtural address, thus the PC don't need to change when
   MMU is enabled. Also the text section is all allocated in cacheable memory,
   which may increase excecution performance.

 - Since this SDRAM allocation avoid overlap in physical memory between
   cacheable and uncacheable memory, the implementation of __ioremap can be
   ignored

Signed-off-by: Eric Sun <jian.sun@freescale.com>

3 files changed, 182 insertions, 3 deletions

diff --git a/board/freescale/mx6q_arm2/config.mk b/board/freescale/mx6q_arm2/config.mk
index a0ce2a1..689d287 100644
--- a/board/freescale/mx6q_arm2/config.mk
+++ b/board/freescale/mx6q_arm2/config.mk
@@ -5,3 +5,7 @@ sinclude $(OBJTREE)/board/$(VENDOR)/$(BOARD)/config.tmp
 ifndef TEXT_BASE
 	TEXT_BASE = 0x27800000
 endif
+
+ifdef CONFIG_MX6Q_ARM2_LPDDR2POP
+	TEXT_BASE = 0x10800000
+endif
diff --git a/board/freescale/mx6q_arm2/flash_header.S b/board/freescale/mx6q_arm2/flash_header.S
index b77a718..a1836e8 100644
--- a/board/freescale/mx6q_arm2/flash_header.S
+++ b/board/freescale/mx6q_arm2/flash_header.S
@@ -57,7 +57,6 @@ image_len:        .word _end_of_copy  - TEXT_BASE + CONFIG_FLASH_HEADER_OFFSET
 plugin:           .word 0x0
 
 #ifdef CONFIG_LPDDR2
-
 dcd_hdr:          .word 0x400804D2 /* Tag=0xD2, Len=128*8 + 4 + 4, Ver=0x40 */
 write_dcd_cmd:    .word 0x040404CC /* Tag=0xCC, Len=128*8 + 4, Param=0x04 */
 
@@ -230,8 +229,147 @@ MXC_DCD_ITEM(126, IOMUXC_BASE_ADDR + 0x010, 0xf00000ff)
 MXC_DCD_ITEM(127, IOMUXC_BASE_ADDR + 0x018, 0x007f007f)
 MXC_DCD_ITEM(128, IOMUXC_BASE_ADDR + 0x01c, 0x007f007f)
 
+#elif defined CONFIG_LPDDR2POP
+dcd_hdr:          .word 0x40F003D2 /* Tag=0xD2, Len=125*8 + 4 + 4, Ver=0x40 */
+write_dcd_cmd:    .word 0x04E403CC /* Tag=0xCC, Len=125*8 + 4, Param=0x04 */
+
+# CCM_BASE_ADDR = 0x020c4000
+MXC_DCD_ITEM(1, CCM_BASE_ADDR + 0x068, 0xffffffff)
+MXC_DCD_ITEM(2, CCM_BASE_ADDR + 0x06c, 0xffffffff)
+MXC_DCD_ITEM(3, CCM_BASE_ADDR + 0x070, 0xffffffff)
+MXC_DCD_ITEM(4, CCM_BASE_ADDR + 0x074, 0xffffffff)
+MXC_DCD_ITEM(5, CCM_BASE_ADDR + 0x078, 0xffffffff)
+MXC_DCD_ITEM(6, CCM_BASE_ADDR + 0x07c, 0xffffffff)
+MXC_DCD_ITEM(7, CCM_BASE_ADDR + 0x080, 0xffffffff)
+MXC_DCD_ITEM(8, CCM_BASE_ADDR + 0x084, 0xffffffff)
+
+#Switch PL301_FAST2 to DDR Dual-channel mapping
+#However, it is not accessable by DCD, consider put it later in "dram_init"
+# GPV0_BASE_ADDR = 0x00B00000
+/*MXC_DCD_ITEM(9, GPV0_BASE_ADDR, 0x00000001)*/
+
+# IOMUXC_BASE_ADDR  = 0x20e0000
+MXC_DCD_ITEM(9, IOMUXC_BASE_ADDR + 0x774, 0x00020000)
+MXC_DCD_ITEM(10, IOMUXC_BASE_ADDR + 0x758, 0x00000000)
+MXC_DCD_ITEM(11, IOMUXC_BASE_ADDR + 0x588, 0x00000038)
+MXC_DCD_ITEM(12, IOMUXC_BASE_ADDR + 0x594, 0x00000038)
+MXC_DCD_ITEM(13, IOMUXC_BASE_ADDR + 0x56c, 0x00000038)
+MXC_DCD_ITEM(14, IOMUXC_BASE_ADDR + 0x578, 0x00000038)
+MXC_DCD_ITEM(15, IOMUXC_BASE_ADDR + 0x57c, 0x00000038)
+MXC_DCD_ITEM(16, IOMUXC_BASE_ADDR + 0x590, 0x00000038)
+MXC_DCD_ITEM(17, IOMUXC_BASE_ADDR + 0x598, 0x00000038)
+MXC_DCD_ITEM(18, IOMUXC_BASE_ADDR + 0x58c, 0x00000000)
+MXC_DCD_ITEM(19, IOMUXC_BASE_ADDR + 0x59c, 0x00000038)
+MXC_DCD_ITEM(20, IOMUXC_BASE_ADDR + 0x5a0, 0x00000038)
+MXC_DCD_ITEM(21, IOMUXC_BASE_ADDR + 0x74c, 0x00000038)
+MXC_DCD_ITEM(22, IOMUXC_BASE_ADDR + 0x78c, 0x00000038)
+MXC_DCD_ITEM(23, IOMUXC_BASE_ADDR + 0x750, 0x00020000)
+MXC_DCD_ITEM(24, IOMUXC_BASE_ADDR + 0x5a8, 0x00003038)
+MXC_DCD_ITEM(25, IOMUXC_BASE_ADDR + 0x5b0, 0x00003038)
+MXC_DCD_ITEM(26, IOMUXC_BASE_ADDR + 0x524, 0x00003038)
+MXC_DCD_ITEM(27, IOMUXC_BASE_ADDR + 0x51c, 0x00003038)
+MXC_DCD_ITEM(28, IOMUXC_BASE_ADDR + 0x518, 0x00003038)
+MXC_DCD_ITEM(29, IOMUXC_BASE_ADDR + 0x50c, 0x00003038)
+MXC_DCD_ITEM(30, IOMUXC_BASE_ADDR + 0x5b8, 0x00003038)
+MXC_DCD_ITEM(31, IOMUXC_BASE_ADDR + 0x5c0, 0x00003038)
+MXC_DCD_ITEM(32, IOMUXC_BASE_ADDR + 0x798, 0x00080000)
+MXC_DCD_ITEM(33, IOMUXC_BASE_ADDR + 0x784, 0x00000038)
+MXC_DCD_ITEM(34, IOMUXC_BASE_ADDR + 0x788, 0x00000038)
+MXC_DCD_ITEM(35, IOMUXC_BASE_ADDR + 0x794, 0x00000038)
+MXC_DCD_ITEM(36, IOMUXC_BASE_ADDR + 0x79c, 0x00000038)
+MXC_DCD_ITEM(37, IOMUXC_BASE_ADDR + 0x7a0, 0x00000038)
+MXC_DCD_ITEM(38, IOMUXC_BASE_ADDR + 0x7a4, 0x00000038)
+MXC_DCD_ITEM(39, IOMUXC_BASE_ADDR + 0x7a8, 0x00000038)
+MXC_DCD_ITEM(40, IOMUXC_BASE_ADDR + 0x748, 0x00000038)
+MXC_DCD_ITEM(41, IOMUXC_BASE_ADDR + 0x5ac, 0x00000038)
+MXC_DCD_ITEM(42, IOMUXC_BASE_ADDR + 0x5b4, 0x00000038)
+MXC_DCD_ITEM(43, IOMUXC_BASE_ADDR + 0x528, 0x00000038)
+MXC_DCD_ITEM(44, IOMUXC_BASE_ADDR + 0x520, 0x00000038)
+MXC_DCD_ITEM(45, IOMUXC_BASE_ADDR + 0x514, 0x00000038)
+MXC_DCD_ITEM(46, IOMUXC_BASE_ADDR + 0x510, 0x00000038)
+MXC_DCD_ITEM(47, IOMUXC_BASE_ADDR + 0x5bc, 0x00000038)
+MXC_DCD_ITEM(48, IOMUXC_BASE_ADDR + 0x5c4, 0x00000038)
+
+# MMDC_P0_BASE_ADDR = 0x021b0000
+# MMDC_P1_BASE_ADDR = 0x021b4000
+MXC_DCD_ITEM(49, MMDC_P0_BASE_ADDR + 0x01c, 0x00008000)
+MXC_DCD_ITEM(50, MMDC_P1_BASE_ADDR + 0x01c, 0x00008000)
+MXC_DCD_ITEM(51, MMDC_P0_BASE_ADDR + 0x85c, 0x1b5f01ff)
+MXC_DCD_ITEM(52, MMDC_P1_BASE_ADDR + 0x85c, 0x1b5f01ff)
+MXC_DCD_ITEM(53, MMDC_P0_BASE_ADDR + 0x800, 0xa1390000)
+MXC_DCD_ITEM(54, MMDC_P1_BASE_ADDR + 0x800, 0xa1390000)
+MXC_DCD_ITEM(55, MMDC_P1_BASE_ADDR + 0x8bc, 0x00055555)
+MXC_DCD_ITEM(56, MMDC_P0_BASE_ADDR + 0x8b8, 0x00000800)
+MXC_DCD_ITEM(57, MMDC_P1_BASE_ADDR + 0x8b8, 0x00000800)
+MXC_DCD_ITEM(58, MMDC_P1_BASE_ADDR + 0x81c, 0x33333333)
+MXC_DCD_ITEM(59, MMDC_P1_BASE_ADDR + 0x820, 0x33333333)
+MXC_DCD_ITEM(60, MMDC_P1_BASE_ADDR + 0x824, 0x33333333)
+MXC_DCD_ITEM(61, MMDC_P1_BASE_ADDR + 0x828, 0x33333303)
+MXC_DCD_ITEM(62, MMDC_P0_BASE_ADDR + 0x82c, 0xf3333333)
+MXC_DCD_ITEM(63, MMDC_P0_BASE_ADDR + 0x830, 0xf3333333)
+MXC_DCD_ITEM(64, MMDC_P0_BASE_ADDR + 0x834, 0xf3333333)
+MXC_DCD_ITEM(65, MMDC_P0_BASE_ADDR + 0x838, 0xf3333333)
+MXC_DCD_ITEM(66, MMDC_P1_BASE_ADDR + 0x82c, 0xf3333333)
+MXC_DCD_ITEM(67, MMDC_P1_BASE_ADDR + 0x830, 0xf3333333)
+MXC_DCD_ITEM(68, MMDC_P1_BASE_ADDR + 0x834, 0xf3333333)
+MXC_DCD_ITEM(69, MMDC_P1_BASE_ADDR + 0x838, 0xf3333303)
+MXC_DCD_ITEM(70, MMDC_P0_BASE_ADDR + 0x848, 0x39313035)
+MXC_DCD_ITEM(71, MMDC_P1_BASE_ADDR + 0x848, 0x39313c42)
+MXC_DCD_ITEM(72, MMDC_P0_BASE_ADDR + 0x850, 0x2e424a44)
+MXC_DCD_ITEM(73, MMDC_P1_BASE_ADDR + 0x850, 0x4c374640)
+MXC_DCD_ITEM(74, MMDC_P0_BASE_ADDR + 0x83c, 0x20000000)
+MXC_DCD_ITEM(75, MMDC_P0_BASE_ADDR + 0x840, 0x00000000)
+MXC_DCD_ITEM(76, MMDC_P1_BASE_ADDR + 0x83c, 0x20000000)
+MXC_DCD_ITEM(77, MMDC_P1_BASE_ADDR + 0x840, 0x00000000)
+MXC_DCD_ITEM(78, MMDC_P0_BASE_ADDR + 0x8b8, 0x00000800)
+MXC_DCD_ITEM(79, MMDC_P1_BASE_ADDR + 0x8b8, 0x00000800)
+MXC_DCD_ITEM(80, MMDC_P0_BASE_ADDR + 0x00c, 0x555A61A5)
+MXC_DCD_ITEM(81, MMDC_P0_BASE_ADDR + 0x004, 0x00020036)
+MXC_DCD_ITEM(82, MMDC_P0_BASE_ADDR + 0x010, 0x00160E83)
+MXC_DCD_ITEM(83, MMDC_P0_BASE_ADDR + 0x014, 0x000000DD)
+MXC_DCD_ITEM(84, MMDC_P0_BASE_ADDR + 0x018, 0x0000174C)
+MXC_DCD_ITEM(85, MMDC_P0_BASE_ADDR + 0x02c, 0x0f9f26d2)
+MXC_DCD_ITEM(86, MMDC_P0_BASE_ADDR + 0x030, 0x0000020e)
+MXC_DCD_ITEM(87, MMDC_P0_BASE_ADDR + 0x038, 0x00220aac)
+MXC_DCD_ITEM(88, MMDC_P0_BASE_ADDR + 0x008, 0x00000000)
+MXC_DCD_ITEM(89, MMDC_P0_BASE_ADDR + 0x040, 0x0000005f)
+MXC_DCD_ITEM(90, MMDC_P0_BASE_ADDR + 0x000, 0xc3010000)
+MXC_DCD_ITEM(91, MMDC_P1_BASE_ADDR + 0x00c, 0x555A61A5)
+MXC_DCD_ITEM(92, MMDC_P1_BASE_ADDR + 0x004, 0x00020036)
+MXC_DCD_ITEM(93, MMDC_P1_BASE_ADDR + 0x010, 0x00160E83)
+MXC_DCD_ITEM(94, MMDC_P1_BASE_ADDR + 0x014, 0x000000DD)
+MXC_DCD_ITEM(95, MMDC_P1_BASE_ADDR + 0x018, 0x0000174C)
+MXC_DCD_ITEM(96, MMDC_P1_BASE_ADDR + 0x02c, 0x0f9f26d2)
+MXC_DCD_ITEM(97, MMDC_P1_BASE_ADDR + 0x030, 0x0000020e)
+MXC_DCD_ITEM(98, MMDC_P1_BASE_ADDR + 0x038, 0x00220aac)
+MXC_DCD_ITEM(99, MMDC_P1_BASE_ADDR + 0x008, 0x00000000)
+MXC_DCD_ITEM(100, MMDC_P1_BASE_ADDR + 0x040, 0x0000003f)
+MXC_DCD_ITEM(101, MMDC_P1_BASE_ADDR + 0x000, 0xc3010000)
+MXC_DCD_ITEM(102, MMDC_P0_BASE_ADDR + 0x01c, 0x003f8030)
+MXC_DCD_ITEM(103, MMDC_P0_BASE_ADDR + 0x01c, 0xff0a8030)
+MXC_DCD_ITEM(104, MMDC_P0_BASE_ADDR + 0x01c, 0xc2018030)
+MXC_DCD_ITEM(105, MMDC_P0_BASE_ADDR + 0x01c, 0x06028030)
+MXC_DCD_ITEM(106, MMDC_P0_BASE_ADDR + 0x01c, 0x01038030)
+MXC_DCD_ITEM(107, MMDC_P1_BASE_ADDR + 0x01c, 0x003f8030)
+MXC_DCD_ITEM(108, MMDC_P1_BASE_ADDR + 0x01c, 0xff0a8030)
+MXC_DCD_ITEM(109, MMDC_P1_BASE_ADDR + 0x01c, 0xc2018030)
+MXC_DCD_ITEM(110, MMDC_P1_BASE_ADDR + 0x01c, 0x06028030)
+MXC_DCD_ITEM(111, MMDC_P1_BASE_ADDR + 0x01c, 0x01038030)
+MXC_DCD_ITEM(112, MMDC_P0_BASE_ADDR + 0x800, 0xa1390003)
+MXC_DCD_ITEM(113, MMDC_P1_BASE_ADDR + 0x800, 0xa1390003)
+MXC_DCD_ITEM(114, MMDC_P0_BASE_ADDR + 0x020, 0x00007800)
+MXC_DCD_ITEM(115, MMDC_P1_BASE_ADDR + 0x020, 0x00007800)
+MXC_DCD_ITEM(116, MMDC_P0_BASE_ADDR + 0x818, 0x00000000)
+MXC_DCD_ITEM(117, MMDC_P1_BASE_ADDR + 0x818, 0x00000000)
+MXC_DCD_ITEM(118, MMDC_P0_BASE_ADDR + 0x8b8, 0x00000800)
+MXC_DCD_ITEM(119, MMDC_P1_BASE_ADDR + 0x8b8, 0x00000800)
+MXC_DCD_ITEM(120, MMDC_P0_BASE_ADDR + 0x004, 0x00025576)
+MXC_DCD_ITEM(121, MMDC_P1_BASE_ADDR + 0x004, 0x00025576)
+MXC_DCD_ITEM(122, MMDC_P0_BASE_ADDR + 0x404, 0x00011006)
+MXC_DCD_ITEM(123, MMDC_P1_BASE_ADDR + 0x404, 0x00011006)
+MXC_DCD_ITEM(124, MMDC_P0_BASE_ADDR + 0x01c, 0x00000000)
+MXC_DCD_ITEM(125, MMDC_P1_BASE_ADDR + 0x01c, 0x00000000)
 #else
-
 dcd_hdr:          .word 0x40F002D2 /* Tag=0xD2, Len=93*8 + 4 + 4, Ver=0x40 */
 write_dcd_cmd:    .word 0x04EC02CC /* Tag=0xCC, Len=93*8 + 4, Param=0x04 */
 
@@ -358,6 +496,7 @@ MXC_DCD_ITEM(93, IOMUXC_BASE_ADDR + 0x01c, 0x007f007f)
 
 
 #else
+
 /*****************PLUGIN IN mode********************/
 
 /*DDR clock:480MHz, ipg clock:40MHz, AHB clock:80MHz*/
@@ -402,7 +541,6 @@ plugin_start:
  * Note: The DDR settings provided below are specific to Freescale development boards and are the latest settings at the time of release.
  * However, it is recommended to contact your Freescale representative in case there are any improvements to these settings.
  */
-
 #ifdef CONFIG_IPG_40M_FR_PLL3
     /*select pll3 for ipg clk 40M */
     ldr r0, =CCM_BASE_ADDR
diff --git a/board/freescale/mx6q_arm2/mx6q_arm2.c b/board/freescale/mx6q_arm2/mx6q_arm2.c
index d97f7b8..c5ff728 100644
--- a/board/freescale/mx6q_arm2/mx6q_arm2.c
+++ b/board/freescale/mx6q_arm2/mx6q_arm2.c
@@ -180,6 +180,7 @@ void board_mmu_init(void)
 	X_ARM_MMU_SECTION(0x00A, 0x00A, 0x0F6,
 			ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
 			ARM_ACCESS_PERM_RW_RW); /* 246M */
+#ifndef CONFIG_MX6Q_ARM2_LPDDR2POP
 	/* 2 GB memory starting at 0x10000000, only map 1.875 GB */
 	X_ARM_MMU_SECTION(0x100, 0x100, 0x780,
 			ARM_CACHEABLE, ARM_BUFFERABLE,
@@ -188,6 +189,29 @@ void board_mmu_init(void)
 	X_ARM_MMU_SECTION(0x100, 0x880, 0x780,
 			ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
 			ARM_ACCESS_PERM_RW_RW);
+#else
+	/*
+	 * Phys		Virtual		Size		Property
+	 * ----------	----------	--------	----------
+	 * 0x10000000	0x10000000	256M		cacheable
+	 * 0x80000000	0x20000000	16M		uncacheable
+	 * 0x81000000	0x21000000	240M		cacheable
+	 */
+	/* Reserve the first 256MB of bank 1 as cacheable memory */
+	X_ARM_MMU_SECTION(0x100, 0x100, 0x100,
+			ARM_CACHEABLE, ARM_BUFFERABLE,
+			ARM_ACCESS_PERM_RW_RW);
+
+	/* Reserve the first 16MB of bank 2 uncachable memory*/
+	X_ARM_MMU_SECTION(0x800, 0x200, 0x010,
+			ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
+			ARM_ACCESS_PERM_RW_RW);
+
+	/* Reserve the remaining 240MB of bank 2 as cacheable memory */
+	X_ARM_MMU_SECTION(0x810, 0x210, 0x0F0,
+			ARM_CACHEABLE, ARM_BUFFERABLE,
+			ARM_ACCESS_PERM_RW_RW);
+#endif
 
 	/* Enable MMU */
 	MMU_ON();
@@ -254,8 +278,21 @@ int setup_sata(void)
 
 int dram_init(void)
 {
+	/*
+	 * Switch PL301_FAST2 to DDR Dual-channel mapping
+	 * however this block the boot up, temperory redraw
+	 */
+	/*
+	 * u32 reg = 1;
+	 * writel(reg, GPV0_BASE_ADDR);
+	 */
+
 	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+#ifdef CONFIG_MX6Q_ARM2_LPDDR2POP
+	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+	gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
+#endif
 	return 0;
 }