ENGR00175117 [MX6DL LPDDR2 Board] Apply Initializtion script and enable U-Boot

Apply script "Mx6DL_init_LPDDR2_400MHz_Micron_1.1.inc" in IVT, make U-boot
work for the LPDDR2 Board. The Make target name for the new board is
"MX6DL_ARM2_LPDDR2_CONFIG"

The script is provided by Chen Wei - B26879 for a quick bring up, which don't
have a corresponding compass link. It is uploaded to CR ticket page for
reference.

Originally for MX6DL DDR3 board, "CONFIG_MX6DL" is defined. It is used by
"board/freescale/mx6q_arm2/flash_header.S" to select the correct IVT. Since
MX6DL LPDDR2 board also define this macro, for distiguish purpose, another
2 macros "CONFIG_MX6DL_DDR3", "CONFIG_MX6DL_LDPPR2" are defined

Signed-off-by: Eric Sun <jian.sun@freescale.com>

1 files changed, 306 insertions, 1 deletions

diff --git a/board/freescale/mx6q_arm2/flash_header.S b/board/freescale/mx6q_arm2/flash_header.S
index 8254179..c6cb83f 100644
--- a/board/freescale/mx6q_arm2/flash_header.S
+++ b/board/freescale/mx6q_arm2/flash_header.S
@@ -56,7 +56,7 @@ boot_data:        .word TEXT_BASE
 image_len:        .word _end_of_copy  - TEXT_BASE + CONFIG_FLASH_HEADER_OFFSET
 plugin:           .word 0x0
 
-#if defined CONFIG_MX6DL
+#if defined CONFIG_MX6DL_DDR3
 dcd_hdr:          .word 0x40F802D2 /* Tag=0xD2, Len=94*8 + 4 + 4, Ver=0x40 */
 write_dcd_cmd:    .word 0x04F402CC /* Tag=0xCC, Len=94*8 + 4, Param=0x04 */
 
@@ -192,6 +192,311 @@ MXC_DCD_ITEM(92, IOMUXC_BASE_ADDR + 0x010, 0xf00000ff)
 MXC_DCD_ITEM(93, IOMUXC_BASE_ADDR + 0x018, 0x007f007f)
 MXC_DCD_ITEM(94, IOMUXC_BASE_ADDR + 0x01c, 0x007f007f)
 
+#elif defined CONFIG_MX6DL_LPDDR2
+
+dcd_hdr:          .word 0x408803D2 /* Tag=0xD2, Len=112*8 + 4 + 4, Ver=0x40 */
+write_dcd_cmd:    .word 0x048403CC /* Tag=0xCC, Len=112*8 + 4, Param=0x04 */
+
+# IOMUX SETTINGS
+# IOMUXC_BASE_ADDR = 0x020e0000
+/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0 */
+MXC_DCD_ITEM(1, IOMUXC_BASE_ADDR + 0x4bc, 0x00003028)
+/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1 */
+MXC_DCD_ITEM(2, IOMUXC_BASE_ADDR + 0x4c0, 0x00003028)
+/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2 */
+MXC_DCD_ITEM(3, IOMUXC_BASE_ADDR + 0x4c4, 0x00003028)
+/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3 */
+MXC_DCD_ITEM(4, IOMUXC_BASE_ADDR + 0x4c8, 0x00003028)
+/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4 */
+MXC_DCD_ITEM(5, IOMUXC_BASE_ADDR + 0x4cc, 0x00003028)
+/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5 */
+MXC_DCD_ITEM(6, IOMUXC_BASE_ADDR + 0x4d0, 0x00003028)
+/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6 */
+MXC_DCD_ITEM(7, IOMUXC_BASE_ADDR + 0x4d4, 0x00003028)
+/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7 */
+MXC_DCD_ITEM(8, IOMUXC_BASE_ADDR + 0x4d8, 0x00003028)
+
+/* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0 */
+MXC_DCD_ITEM(9, IOMUXC_BASE_ADDR + 0x470, 0x00000038)
+/* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1 */
+MXC_DCD_ITEM(10, IOMUXC_BASE_ADDR + 0x474, 0x00000038)
+/* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2 */
+MXC_DCD_ITEM(11, IOMUXC_BASE_ADDR + 0x478, 0x00000038)
+/* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3 */
+MXC_DCD_ITEM(12, IOMUXC_BASE_ADDR + 0x47c, 0x00000038)
+/* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4 */
+MXC_DCD_ITEM(13, IOMUXC_BASE_ADDR + 0x480, 0x00000038)
+/* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5 */
+MXC_DCD_ITEM(14, IOMUXC_BASE_ADDR + 0x484, 0x00000038)
+/* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6 */
+MXC_DCD_ITEM(15, IOMUXC_BASE_ADDR + 0x488, 0x00000038)
+/* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7 */
+MXC_DCD_ITEM(16, IOMUXC_BASE_ADDR + 0x48c, 0x00000038)
+/* IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS */
+MXC_DCD_ITEM(17, IOMUXC_BASE_ADDR + 0x464, 0x00000038)
+/* IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS */
+MXC_DCD_ITEM(18, IOMUXC_BASE_ADDR + 0x490, 0x00000038)
+/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_0 */
+MXC_DCD_ITEM(19, IOMUXC_BASE_ADDR + 0x4ac, 0x00000038)
+/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_1 */
+MXC_DCD_ITEM(20, IOMUXC_BASE_ADDR + 0x4b0, 0x00000038)
+/* IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET */
+MXC_DCD_ITEM(21, IOMUXC_BASE_ADDR + 0x494, 0x00000038)
+/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0 */
+MXC_DCD_ITEM(22, IOMUXC_BASE_ADDR + 0x4a4, 0x00000038)
+/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1 */
+MXC_DCD_ITEM(23, IOMUXC_BASE_ADDR + 0x4a8, 0x00000038)
+/*
+ * IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2
+ * DSE can be configured using Group Control Register:
+ * IOMUXC_SW_PAD_CTL_GRP_CTLDS
+ */
+MXC_DCD_ITEM(24, IOMUXC_BASE_ADDR + 0x4a0, 0x00000000)
+/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT0 */
+MXC_DCD_ITEM(25, IOMUXC_BASE_ADDR + 0x4b4, 0x00000038)
+/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT1 */
+MXC_DCD_ITEM(26, IOMUXC_BASE_ADDR + 0x4b8, 0x00000038)
+/* IOMUXC_SW_PAD_CTL_GRP_B0DS */
+MXC_DCD_ITEM(27, IOMUXC_BASE_ADDR + 0x764, 0x00000038)
+/* IOMUXC_SW_PAD_CTL_GRP_B1DS */
+MXC_DCD_ITEM(28, IOMUXC_BASE_ADDR + 0x770, 0x00000038)
+/* IOMUXC_SW_PAD_CTL_GRP_B2DS */
+MXC_DCD_ITEM(29, IOMUXC_BASE_ADDR + 0x778, 0x00000038)
+/* IOMUXC_SW_PAD_CTL_GRP_B3DS */
+MXC_DCD_ITEM(30, IOMUXC_BASE_ADDR + 0x77c, 0x00000038)
+/* IOMUXC_SW_PAD_CTL_GRP_B4DS */
+MXC_DCD_ITEM(31, IOMUXC_BASE_ADDR + 0x780, 0x00000038)
+/* IOMUXC_SW_PAD_CTL_GRP_B5DS */
+MXC_DCD_ITEM(32, IOMUXC_BASE_ADDR + 0x784, 0x00000038)
+/* IOMUXC_SW_PAD_CTL_GRP_B6DS */
+MXC_DCD_ITEM(33, IOMUXC_BASE_ADDR + 0x78c, 0x00000038)
+/* IOMUXC_SW_PAD_CTL_GRP_B7DS */
+MXC_DCD_ITEM(34, IOMUXC_BASE_ADDR + 0x748, 0x00000038)
+/* IOMUXC_SW_PAD_CTL_GRP_ADDDS */
+MXC_DCD_ITEM(35, IOMUXC_BASE_ADDR + 0x74c, 0x00000038)
+/* IOMUXC_SW_PAD_CTL_GRP_CTLDS */
+MXC_DCD_ITEM(36, IOMUXC_BASE_ADDR + 0x76c, 0x00000038)
+/* IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL */
+MXC_DCD_ITEM(37, IOMUXC_BASE_ADDR + 0x750, 0x00020000)
+/* IOMUXC_SW_PAD_CTL_GRP_DDRPKE */
+MXC_DCD_ITEM(38, IOMUXC_BASE_ADDR + 0x754, 0x00000000)
+/* IOMUXC_SW_PAD_CTL_GRP_DDRMODE */
+MXC_DCD_ITEM(39, IOMUXC_BASE_ADDR + 0x760, 0x00020000)
+/* IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE */
+MXC_DCD_ITEM(40, IOMUXC_BASE_ADDR + 0x774, 0x00080000)
+
+/*
+ * DDR Controller Registers
+ *
+ * Manufacturer:	Mocron
+ * Device Part Number:	MT42L64M64D2KH-18
+ * Clock Freq.: 	528MHz
+ * MMDC channels: Both MMDC0, MMDC1
+ *Density per CS in Gb: 	256M
+ * Chip Selects used:	2
+ * Number of Banks:	8
+ * Row address:    	14
+ * Column address: 	9
+ * Data bus width	32
+ */
+
+# MMDC_P0_BASE_ADDR = 0x021b0000
+# MMDC_P1_BASE_ADDR = 0x021b4000
+
+/* MMDC0_MDSCR, set the Configuration request bit during MMDC set up */
+MXC_DCD_ITEM(41, MMDC_P0_BASE_ADDR + 0x01c, 0x00008000)
+
+/* MMDC0_MDSCR, set the Configuration request bit during MMDC set up */
+MXC_DCD_ITEM(42, MMDC_P1_BASE_ADDR + 0x01c, 0x00008000)
+
+/*LPDDR2 ZQ params */
+MXC_DCD_ITEM(43, MMDC_P0_BASE_ADDR + 0x85c, 0x1b5f01ff)
+MXC_DCD_ITEM(44, MMDC_P1_BASE_ADDR + 0x85c, 0x1b5f01ff)
+
+# Calibration setup.
+/* DDR_PHY_P0_MPZQHWCTRL, enable on time ZQ calibration */
+MXC_DCD_ITEM(45, MMDC_P0_BASE_ADDR + 0x800, 0xa1390003)
+
+/*ca bus abs delay */
+MXC_DCD_ITEM(46, MMDC_P0_BASE_ADDR + 0x890, 0x00400000)
+/*ca bus abs delay */
+MXC_DCD_ITEM(47, MMDC_P1_BASE_ADDR + 0x890, 0x00400000)
+/* values of 20,40,50,60,7f tried. no difference seen */
+
+/* DDR_PHY_P1_MPWRCADL */
+MXC_DCD_ITEM(48, MMDC_P1_BASE_ADDR + 0x8bc, 0x00055555)
+
+/*frc_msr.*/
+MXC_DCD_ITEM(49, MMDC_P0_BASE_ADDR + 0x8b8, 0x00000800)
+/*frc_msr.*/
+MXC_DCD_ITEM(50, MMDC_P1_BASE_ADDR + 0x8b8, 0x00000800)
+
+/* DDR_PHY_P0_MPREDQBY0DL3 */
+MXC_DCD_ITEM(51, MMDC_P0_BASE_ADDR + 0x81c, 0x33333333)
+/* DDR_PHY_P0_MPREDQBY1DL3 */
+MXC_DCD_ITEM(52, MMDC_P0_BASE_ADDR + 0x820, 0x33333333)
+/* DDR_PHY_P0_MPREDQBY2DL3 */
+MXC_DCD_ITEM(53, MMDC_P0_BASE_ADDR + 0x824, 0x33333333)
+/* DDR_PHY_P0_MPREDQBY3DL3 */
+MXC_DCD_ITEM(54, MMDC_P0_BASE_ADDR + 0x828, 0x33333333)
+/* DDR_PHY_P1_MPREDQBY0DL3 */
+MXC_DCD_ITEM(55, MMDC_P1_BASE_ADDR + 0x81c, 0x33333333)
+/* DDR_PHY_P1_MPREDQBY1DL3 */
+MXC_DCD_ITEM(56, MMDC_P1_BASE_ADDR + 0x820, 0x33333333)
+/* DDR_PHY_P1_MPREDQBY2DL3 */
+MXC_DCD_ITEM(57, MMDC_P1_BASE_ADDR + 0x824, 0x33333333)
+/* DDR_PHY_P1_MPREDQBY3DL3 */
+MXC_DCD_ITEM(58, MMDC_P1_BASE_ADDR + 0x828, 0x33333333)
+
+/*
+ * Read and write data delay, per byte.
+ * For optimized DDR operation it is recommended to run mmdc_calibration
+ * on your board, and replace 4 delay register assigns with resulted values
+ * Note:
+ * a. DQS gating is not relevant for LPDDR2. DSQ gating calibration section
+ *    should be skipped, or the write/read calibration comming after that
+ *    will stall
+ * b. The calibration code that runs for both MMDC0 & MMDC1 should be used.
+ */
+
+MXC_DCD_ITEM(59, MMDC_P0_BASE_ADDR + 0x848, 0x4b4b524f)
+MXC_DCD_ITEM(60, MMDC_P1_BASE_ADDR + 0x848, 0x494f4c44)
+
+MXC_DCD_ITEM(61, MMDC_P0_BASE_ADDR + 0x850, 0x3c3d303c)
+MXC_DCD_ITEM(62, MMDC_P1_BASE_ADDR + 0x850, 0x3c343d38)
+
+/*dqs gating dis */
+MXC_DCD_ITEM(63, MMDC_P0_BASE_ADDR + 0x83c, 0x20000000)
+MXC_DCD_ITEM(64, MMDC_P0_BASE_ADDR + 0x840, 0x0)
+MXC_DCD_ITEM(65, MMDC_P1_BASE_ADDR + 0x83c, 0x20000000)
+MXC_DCD_ITEM(66, MMDC_P1_BASE_ADDR + 0x840, 0x0)
+
+/*clk delay */
+MXC_DCD_ITEM(67, MMDC_P0_BASE_ADDR + 0x858, 0xa00)
+/*clk delay */
+MXC_DCD_ITEM(68, MMDC_P1_BASE_ADDR + 0x858, 0xa00)
+
+/*frc_msr */
+MXC_DCD_ITEM(69, MMDC_P0_BASE_ADDR + 0x8b8, 0x00000800)
+/*frc_msr */
+MXC_DCD_ITEM(70, MMDC_P1_BASE_ADDR + 0x8b8, 0x00000800)
+# Calibration setup end
+
+/* Channel0 - startng address 0x80000000 */
+/* MMDC0_MDCFG0 */
+MXC_DCD_ITEM(71, MMDC_P0_BASE_ADDR + 0x00c, 0x34386145)
+
+/* MMDC0_MDPDC */
+MXC_DCD_ITEM(72, MMDC_P0_BASE_ADDR + 0x004, 0x00020036)
+/* MMDC0_MDCFG1 */
+MXC_DCD_ITEM(73, MMDC_P0_BASE_ADDR + 0x010, 0x00100c83)
+/* MMDC0_MDCFG2 */
+MXC_DCD_ITEM(74, MMDC_P0_BASE_ADDR + 0x014, 0x000000Dc)
+/* MMDC0_MDMISC */
+MXC_DCD_ITEM(75, MMDC_P0_BASE_ADDR + 0x018, 0x0000174C)
+/* MMDC0_MDRWD;*/
+MXC_DCD_ITEM(76, MMDC_P0_BASE_ADDR + 0x02c, 0x0f9f26d2)
+/* MMDC0_MDOR */
+MXC_DCD_ITEM(77, MMDC_P0_BASE_ADDR + 0x030, 0x0000020e)
+/* MMDC0_MDCFG3LP */
+MXC_DCD_ITEM(78, MMDC_P0_BASE_ADDR + 0x038, 0x00190778)
+/* MMDC0_MDOTC */
+MXC_DCD_ITEM(79, MMDC_P0_BASE_ADDR + 0x008, 0x00000000)
+
+/* CS0_END */
+MXC_DCD_ITEM(80, MMDC_P0_BASE_ADDR + 0x040, 0x0000005f)
+/* ROC */
+MXC_DCD_ITEM(81, MMDC_P0_BASE_ADDR + 0x404, 0x0000000f)
+
+/* MMDC0_MDCTL */
+MXC_DCD_ITEM(82, MMDC_P0_BASE_ADDR + 0x000, 0xc3010000)
+
+/* Channel1 - starting address 0x10000000 */
+/* MMDC1_MDCFG0 */
+MXC_DCD_ITEM(83, MMDC_P1_BASE_ADDR + 0x00c, 0x34386145)
+
+/* MMDC1_MDPDC */
+MXC_DCD_ITEM(84, MMDC_P1_BASE_ADDR + 0x004, 0x00020036)
+/* MMDC1_MDCFG1 */
+MXC_DCD_ITEM(85, MMDC_P1_BASE_ADDR + 0x010, 0x00100c83)
+/* MMDC1_MDCFG2 */
+MXC_DCD_ITEM(86, MMDC_P1_BASE_ADDR + 0x014, 0x000000Dc)
+/* MMDC1_MDMISC */
+MXC_DCD_ITEM(87, MMDC_P1_BASE_ADDR + 0x018, 0x0000174C)
+/* MMDC1_MDRWD;*/
+MXC_DCD_ITEM(88, MMDC_P1_BASE_ADDR + 0x02c, 0x0f9f26d2)
+/* MMDC1_MDOR */
+MXC_DCD_ITEM(89, MMDC_P1_BASE_ADDR + 0x030, 0x0000020e)
+/* MMDC1_MDCFG3LP */
+MXC_DCD_ITEM(90, MMDC_P1_BASE_ADDR + 0x038, 0x00190778)
+/* MMDC1_MDOTC */
+MXC_DCD_ITEM(91, MMDC_P1_BASE_ADDR + 0x008, 0x00000000)
+
+/* CS0_END */
+MXC_DCD_ITEM(92, MMDC_P1_BASE_ADDR + 0x040, 0x0000003f)
+
+/* MMDC1_MDCTL */
+MXC_DCD_ITEM(93, MMDC_P1_BASE_ADDR + 0x000, 0xc3010000)
+
+/* Channel0 : Configure DDR device:*/
+/* MRW: BA=0 CS=0 MR_ADDR=63 MR_OP=0 */
+MXC_DCD_ITEM(94, MMDC_P0_BASE_ADDR + 0x01c, 0x003f8030)
+/* MRW: BA=0 CS=0 MR_ADDR=10 MR_OP=ff */
+MXC_DCD_ITEM(95, MMDC_P0_BASE_ADDR + 0x01c, 0xff0a8030)
+/* MRW: BA=0 CS=0 MR_ADDR=1  MR_OP=a2 */
+MXC_DCD_ITEM(96, MMDC_P0_BASE_ADDR + 0x01c, 0xa2018030)
+/* MRW: BA=0 CS=0 MR_ADDR=2  MR_OP=6. tcl=8, tcwl=4 */
+MXC_DCD_ITEM(97, MMDC_P0_BASE_ADDR + 0x01c, 0x06028030)
+/* MRW: BA=0 CS=0 MR_ADDR=3  MR_OP=2.drive=240/6 */
+MXC_DCD_ITEM(98, MMDC_P0_BASE_ADDR + 0x01c, 0x01038030)
+
+/* Channel1 : Configure DDR device:*/
+/* MRW: BA=0 CS=0 MR_ADDR=63 MR_OP=0 */
+MXC_DCD_ITEM(99, MMDC_P1_BASE_ADDR + 0x01c, 0x003f8030)
+/* MRW: BA=0 CS=0 MR_ADDR=10 MR_OP=ff */
+MXC_DCD_ITEM(100, MMDC_P1_BASE_ADDR + 0x01c, 0xff0a8030)
+/* MRW: BA=0 CS=0 MR_ADDR=1  MR_OP=a2 */
+MXC_DCD_ITEM(101, MMDC_P1_BASE_ADDR + 0x01c, 0xa2018030)
+/* MRW: BA=0 CS=0 MR_ADDR=2  MR_OP=6. tcl=8, tcwl=4 */
+MXC_DCD_ITEM(102, MMDC_P1_BASE_ADDR + 0x01c, 0x06028030)
+/* MRW: BA=0 CS=0 MR_ADDR=3  MR_OP=2.drive=240/6 */
+MXC_DCD_ITEM(103, MMDC_P1_BASE_ADDR + 0x01c, 0x01038030)
+
+/* MMDC0_MDREF */
+MXC_DCD_ITEM(104, MMDC_P0_BASE_ADDR + 0x020, 0x00005800)
+/* MMDC1_MDREF */
+MXC_DCD_ITEM(105, MMDC_P1_BASE_ADDR + 0x020, 0x00005800)
+
+/* DDR_PHY_P0_MPODTCTRL */
+MXC_DCD_ITEM(106, MMDC_P0_BASE_ADDR + 0x818, 0x0)
+/* DDR_PHY_P1_MPODTCTRL */
+MXC_DCD_ITEM(107, MMDC_P1_BASE_ADDR + 0x818, 0x0)
+
+/*
+ * calibration values based on calibration compare of 0x00ffff00:
+ * Note, these calibration values are based on Freescale's board
+ * May need to run calibration on target board to fine tune these
+ */
+
+/* DDR_PHY_P0_MPZQHWCTRL, enable automatic ZQ calibration */
+MXC_DCD_ITEM(108, MMDC_P0_BASE_ADDR + 0x800, 0xa1310003)
+
+/* DDR_PHY_P0_MPMUR0, frc_msr */
+MXC_DCD_ITEM(109, MMDC_P0_BASE_ADDR + 0x8b8, 0x00000800)
+/* DDR_PHY_P1_MPMUR0, frc_msr */
+MXC_DCD_ITEM(110, MMDC_P1_BASE_ADDR + 0x8b8, 0x00000800)
+
+/*
+ * MMDC0_MDSCR, clear this register
+ * (especially the configuration bit as initialization is complete)
+ */
+MXC_DCD_ITEM(111, MMDC_P0_BASE_ADDR + 0x01c, 0x00000000)
+/*
+ * MMDC0_MDSCR, clear this register
+ * (especially the configuration bit as initialization is complete)
+ */
+MXC_DCD_ITEM(112, MMDC_P1_BASE_ADDR + 0x01c, 0x00000000)
+
 #elif defined(CONFIG_LPDDR2)
 dcd_hdr:          .word 0x400804D2 /* Tag=0xD2, Len=128*8 + 4 + 4, Ver=0x40 */
 write_dcd_cmd:    .word 0x040404CC /* Tag=0xCC, Len=128*8 + 4, Param=0x04 */