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authorTimur Tabi <timur@freescale.com>2011-10-18 18:44:34 -0500
committerKumar Gala <galak@kernel.crashing.org>2011-10-20 16:01:37 -0500
commita836626cc4ddae53bfa46195a39194f21ad157af (patch)
tree9fbd99ccbe888bbcaf557d354a31da9ba9d9be25 /board/freescale
parent3b001ad26d6e03ebe2510ec8506a8425392adcf8 (diff)
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powerpc/85xx: wait for alignment before resetting SERDES RX lanes (SERDES9)
The work-around for P4080 erratum SERDES9 says that the SERDES receiver lanes should be reset after the XAUI starts tranmitting alignment signals. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'board/freescale')
-rw-r--r--board/freescale/corenet_ds/eth_p4080.c38
1 files changed, 30 insertions, 8 deletions
diff --git a/board/freescale/corenet_ds/eth_p4080.c b/board/freescale/corenet_ds/eth_p4080.c
index 00dfa9a..7ff00d1 100644
--- a/board/freescale/corenet_ds/eth_p4080.c
+++ b/board/freescale/corenet_ds/eth_p4080.c
@@ -93,21 +93,43 @@ struct mii_dev *mii_dev_for_muxval(u32 muxval)
return bus;
}
-#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES9
+#if defined(CONFIG_SYS_P4080_ERRATUM_SERDES9) && defined(CONFIG_PHY_TERANETICS)
int board_phy_config(struct phy_device *phydev)
{
- /*
- * If this is the 10G PHY, and we switched it to fiber,
- * we need to reset the serdes link for SERDES9
- */
- if ((phydev->port == PORT_FIBRE) && (phydev->drv->uid == 0x00a19410)) {
+ if (phydev->drv->uid == PHY_UID_TN2020) {
+ unsigned long timeout = 1 * 1000; /* 1 seconds */
enum srds_prtcl device;
+ /*
+ * Wait for the XAUI to come out of reset. This is when it
+ * starts transmitting alignment signals.
+ */
+ while (--timeout) {
+ int reg = phy_read(phydev, MDIO_MMD_PHYXS, MDIO_CTRL1);
+ if (reg < 0) {
+ printf("TN2020: Error reading from PHY at "
+ "address %u\n", phydev->addr);
+ break;
+ }
+ /*
+ * Note that we've never actually seen
+ * MDIO_CTRL1_RESET set to 1.
+ */
+ if ((reg & MDIO_CTRL1_RESET) == 0)
+ break;
+ udelay(1000);
+ }
+
+ if (!timeout) {
+ printf("TN2020: Timeout waiting for PHY at address %u "
+ " to reset.\n", phydev->addr);
+ }
+
switch (phydev->addr) {
- case 4:
+ case CONFIG_SYS_FM1_10GEC1_PHY_ADDR:
device = XAUI_FM1;
break;
- case 0:
+ case CONFIG_SYS_FM2_10GEC1_PHY_ADDR:
device = XAUI_FM2;
break;
default: