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authorPeng Fan <peng.fan@nxp.com>2017-02-07 18:24:39 +0800
committerYe Li <ye.li@nxp.com>2017-04-05 17:23:50 +0800
commitdb7d3954b773a2b67e4211606551c06c7573df10 (patch)
treec4c817290e560cf2860a3134b185d6833a6487bf /board/freescale
parentb6122733dee0d857565fecf251f68f050eea3cb9 (diff)
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MLK-14419-2 imx: mx7d_arm2: add 12x12 ddr3 arm2 board support
Add 12x12 ddr3 arm2 board support and convert it to use OF_CONTROL and DM drivers. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com>
Diffstat (limited to 'board/freescale')
-rw-r--r--board/freescale/mx7d_12x12_ddr3_arm2/Kconfig12
-rw-r--r--board/freescale/mx7d_12x12_ddr3_arm2/Makefile6
-rw-r--r--board/freescale/mx7d_12x12_ddr3_arm2/imximage.cfg104
-rw-r--r--board/freescale/mx7d_12x12_ddr3_arm2/imximage_TO_1_1.cfg115
-rw-r--r--board/freescale/mx7d_12x12_ddr3_arm2/mx7d_12x12_ddr3_arm2.c190
-rw-r--r--board/freescale/mx7d_12x12_ddr3_arm2/plugin.S217
6 files changed, 644 insertions, 0 deletions
diff --git a/board/freescale/mx7d_12x12_ddr3_arm2/Kconfig b/board/freescale/mx7d_12x12_ddr3_arm2/Kconfig
new file mode 100644
index 0000000..b1d8c22
--- /dev/null
+++ b/board/freescale/mx7d_12x12_ddr3_arm2/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_MX7D_12X12_DDR3_ARM2
+
+config SYS_BOARD
+ default "mx7d_12x12_ddr3_arm2"
+
+config SYS_VENDOR
+ default "freescale"
+
+config SYS_CONFIG_NAME
+ default "mx7d_12x12_ddr3_arm2"
+
+endif
diff --git a/board/freescale/mx7d_12x12_ddr3_arm2/Makefile b/board/freescale/mx7d_12x12_ddr3_arm2/Makefile
new file mode 100644
index 0000000..6636874
--- /dev/null
+++ b/board/freescale/mx7d_12x12_ddr3_arm2/Makefile
@@ -0,0 +1,6 @@
+# (C) Copyright 2015 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := mx7d_12x12_ddr3_arm2.o
diff --git a/board/freescale/mx7d_12x12_ddr3_arm2/imximage.cfg b/board/freescale/mx7d_12x12_ddr3_arm2/imximage.cfg
new file mode 100644
index 0000000..0c70d39
--- /dev/null
+++ b/board/freescale/mx7d_12x12_ddr3_arm2/imximage.cfg
@@ -0,0 +1,104 @@
+/*
+ * Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Refer doc/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+#define __ASSEMBLY__
+#include <config.h>
+
+/* image version */
+
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * sd/onenand, nor
+ */
+
+BOOT_FROM sd
+
+#ifdef CONFIG_USE_IMXIMG_PLUGIN
+/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/
+PLUGIN board/freescale/mx7d_12x12_ddr3_arm2/plugin.bin 0x00910000
+#else
+
+#ifdef CONFIG_SECURE_BOOT
+CSF CONFIG_CSF_SIZE
+#endif
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type Address Value
+ *
+ * where:
+ * Addr-type register length (1,2 or 4 bytes)
+ * Address absolute address of the register
+ * value value to be stored in the register
+ */
+
+DATA 4 0x30340004 0x4F400005
+
+DATA 4 0x30391000 0x00000002
+DATA 4 0x307a0000 0x03040001
+DATA 4 0x307a01a0 0x80400003
+DATA 4 0x307a01a4 0x00100020
+DATA 4 0x307a01a8 0x80100004
+DATA 4 0x307a0064 0x0040005e
+DATA 4 0x307a0490 0x00000001
+DATA 4 0x307a00d0 0x00020001
+DATA 4 0x307a00d4 0x00010000
+DATA 4 0x307a00dc 0x09300004
+DATA 4 0x307a00e0 0x04080000
+DATA 4 0x307a00e4 0x00090004
+DATA 4 0x307a00f4 0x0000033f
+DATA 4 0x307a0100 0x0908120a
+DATA 4 0x307a0104 0x0002020e
+DATA 4 0x307a0108 0x03040407
+DATA 4 0x307a010c 0x00002006
+DATA 4 0x307a0110 0x04020204
+DATA 4 0x307a0114 0x03030202
+DATA 4 0x307a0120 0x03030803
+DATA 4 0x307a0180 0x00800020
+DATA 4 0x307a0190 0x02098204
+DATA 4 0x307a0194 0x00030303
+DATA 4 0x307a0200 0x00000016
+DATA 4 0x307a0204 0x00171717
+DATA 4 0x307a0214 0x04040404
+DATA 4 0x307a0218 0x00040404
+DATA 4 0x307a0240 0x06000601
+DATA 4 0x307a0244 0x00001323
+DATA 4 0x30391000 0x00000000
+DATA 4 0x30790000 0x17420f40
+DATA 4 0x30790004 0x10210100
+DATA 4 0x30790010 0x00060807
+DATA 4 0x3079009c 0x00000d6e
+DATA 4 0x30790020 0x08080808
+DATA 4 0x30790030 0x08080808
+DATA 4 0x30790050 0x01000010
+DATA 4 0x30790050 0x00000010
+
+DATA 4 0x307900c0 0x0e407304
+DATA 4 0x307900c0 0x0e447304
+DATA 4 0x307900c0 0x0e447306
+
+CHECK_BITS_SET 4 0x307900c4 0x1
+
+DATA 4 0x307900c0 0x0e447304
+DATA 4 0x307900c0 0x0e407304
+
+DATA 4 0x30384130 0x00000000
+DATA 4 0x30340020 0x00000178
+DATA 4 0x30384130 0x00000002
+DATA 4 0x30790018 0x0000000f
+
+CHECK_BITS_SET 4 0x307a0004 0x1
+#endif
diff --git a/board/freescale/mx7d_12x12_ddr3_arm2/imximage_TO_1_1.cfg b/board/freescale/mx7d_12x12_ddr3_arm2/imximage_TO_1_1.cfg
new file mode 100644
index 0000000..62bb99d
--- /dev/null
+++ b/board/freescale/mx7d_12x12_ddr3_arm2/imximage_TO_1_1.cfg
@@ -0,0 +1,115 @@
+/*
+ * Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+#define __ASSEMBLY__
+#include <config.h>
+
+/* image version */
+
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * sd/onenand, nor
+ */
+
+BOOT_FROM sd
+
+#ifdef CONFIG_USE_IMXIMG_PLUGIN
+/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/
+PLUGIN board/freescale/mx7d_12x12_ddr3_arm2/plugin.bin 0x00910000
+#else
+
+#ifdef CONFIG_SECURE_BOOT
+CSF CONFIG_CSF_SIZE
+#endif
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type Address Value
+ *
+ * where:
+ * Addr-type register length (1,2 or 4 bytes)
+ * Address absolute address of the register
+ * value value to be stored in the register
+ */
+
+DATA 4 0x30360070 0x00703021
+DATA 4 0x30360090 0x0
+DATA 4 0x30360070 0x00603021
+CHECK_BITS_SET 4 0x30360070 0x80000000
+DATA 4 0x30389880 0x1
+
+DATA 4 0x30340004 0x4F400005
+
+DATA 4 0x30391000 0x00000002
+DATA 4 0x307a0000 0x03040001
+DATA 4 0x307a01a0 0x80400003
+DATA 4 0x307a01a4 0x00100020
+DATA 4 0x307a01a8 0x80100004
+DATA 4 0x307a0064 0x0040005e
+DATA 4 0x307a0490 0x00000001
+DATA 4 0x307a00d0 0x00020001
+DATA 4 0x307a00d4 0x00010000
+DATA 4 0x307a00dc 0x09300004
+DATA 4 0x307a00e0 0x04080000
+DATA 4 0x307a00e4 0x00090004
+DATA 4 0x307a00f4 0x0000033f
+DATA 4 0x307a0100 0x0908120a
+DATA 4 0x307a0104 0x0002020e
+DATA 4 0x307a0108 0x03040407
+DATA 4 0x307a010c 0x00002006
+DATA 4 0x307a0110 0x04020204
+DATA 4 0x307a0114 0x03030202
+DATA 4 0x307a0120 0x03030803
+DATA 4 0x307a0180 0x00800020
+DATA 4 0x307a0190 0x02098204
+DATA 4 0x307a0194 0x00030303
+DATA 4 0x307a0200 0x00000016
+DATA 4 0x307a0204 0x00171717
+DATA 4 0x307a0214 0x04040404
+DATA 4 0x307a0218 0x00040404
+DATA 4 0x307a0240 0x06000601
+DATA 4 0x307a0244 0x00001323
+DATA 4 0x30391000 0x00000000
+DATA 4 0x30790000 0x17420f40
+DATA 4 0x30790004 0x10210100
+DATA 4 0x30790010 0x00060807
+DATA 4 0x3079009c 0x00000dee
+DATA 4 0x3079007c 0x18181818
+DATA 4 0x30790080 0x18181818
+DATA 4 0x30790084 0x40401818
+DATA 4 0x30790088 0x00000040
+DATA 4 0x3079006c 0x40404040
+DATA 4 0x30790020 0x08080808
+DATA 4 0x30790030 0x08080808
+DATA 4 0x30790050 0x01000010
+DATA 4 0x30790050 0x00000010
+
+DATA 4 0x307900c0 0x0e407304
+DATA 4 0x307900c0 0x0e447304
+DATA 4 0x307900c0 0x0e447306
+
+CHECK_BITS_SET 4 0x307900c4 0x1
+
+DATA 4 0x307900c0 0x0e447304
+DATA 4 0x307900c0 0x0e407304
+
+DATA 4 0x30384130 0x00000000
+DATA 4 0x30340020 0x00000178
+DATA 4 0x30384130 0x00000002
+DATA 4 0x30790018 0x0000000f
+
+CHECK_BITS_SET 4 0x307a0004 0x1
+#endif
diff --git a/board/freescale/mx7d_12x12_ddr3_arm2/mx7d_12x12_ddr3_arm2.c b/board/freescale/mx7d_12x12_ddr3_arm2/mx7d_12x12_ddr3_arm2.c
new file mode 100644
index 0000000..ff07969
--- /dev/null
+++ b/board/freescale/mx7d_12x12_ddr3_arm2/mx7d_12x12_ddr3_arm2.c
@@ -0,0 +1,190 @@
+/*
+ * Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/mx7-pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/imx-common/iomux-v3.h>
+#include <asm/imx-common/boot_mode.h>
+#include <asm/io.h>
+#include <linux/sizes.h>
+#include <common.h>
+#include <fsl_esdhc.h>
+#include <mmc.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <power/pmic.h>
+#include <power/pfuze3000_pmic.h>
+#include "../common/pfuze.h"
+#include <asm/arch/crm_regs.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | \
+ PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS)
+#define USDHC_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \
+ PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM)
+#define SPI_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_SLOW | PAD_CTL_HYS)
+
+int dram_init(void)
+{
+ gd->ram_size = PHYS_SDRAM_SIZE;
+
+ return 0;
+}
+
+static iomux_v3_cfg_t const uart1_pads[] = {
+ MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const wdog_pads[] = {
+ MX7D_PAD_GPIO1_IO00__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static void setup_iomux_uart(void)
+{
+ imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
+}
+
+#ifdef CONFIG_FSL_ESDHC
+int board_mmc_get_env_dev(int devno)
+{
+ return devno - 1;
+}
+
+int mmc_map_to_kernel_blk(int dev_no)
+{
+ return dev_no + 1;
+}
+#endif
+
+#ifdef CONFIG_MXC_SPI
+iomux_v3_cfg_t const ecspi1_pads[] = {
+ MX7D_PAD_SD1_RESET_B__ECSPI4_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
+ MX7D_PAD_SD1_WP__ECSPI4_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
+ MX7D_PAD_SD1_CD_B__ECSPI4_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
+ /* Chip selects CS0:CS3 */
+ MX7D_PAD_SD1_CLK__GPIO5_IO3 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX7D_PAD_SD1_CMD__GPIO5_IO4 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX7D_PAD_SD1_DATA0__GPIO5_IO5 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX7D_PAD_SD1_DATA1__GPIO5_IO6 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+void setup_spinor(void)
+{
+ imx_iomux_v3_setup_multiple_pads(ecspi1_pads,
+ ARRAY_SIZE(ecspi1_pads));
+ gpio_request(IMX_GPIO_NR(5, 3), "ecspi1_cs");
+ gpio_direction_output(IMX_GPIO_NR(5, 3), 0);
+}
+
+int board_spi_cs_gpio(unsigned bus, unsigned cs)
+{
+ return (bus == 3 && cs == 0) ? (IMX_GPIO_NR(5, 3)) : -1;
+}
+#endif
+
+int board_early_init_f(void)
+{
+ setup_iomux_uart();
+
+ return 0;
+}
+
+int board_init(void)
+{
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+#ifdef CONFIG_MXC_SPI
+ setup_spinor();
+#endif
+
+ return 0;
+}
+
+#ifdef CONFIG_CMD_BMODE
+static const struct boot_mode board_boot_modes[] = {
+ /* 4 bit bus width */
+ {"emmc", MAKE_CFGVAL(0x10, 0x22, 0x00, 0x00)},
+ {"sd3", MAKE_CFGVAL(0x10, 0x1a, 0x00, 0x00)},
+ {NULL, 0},
+};
+#endif
+
+#ifdef CONFIG_DM_PMIC
+int power_init_board(void)
+{
+ struct udevice *dev;
+ int ret, dev_id, rev_id, reg;
+
+ ret = pmic_get("pfuze3000", &dev);
+ if (ret == -ENODEV)
+ return 0;
+ if (ret != 0)
+ return ret;
+
+ dev_id = pmic_reg_read(dev, PFUZE3000_DEVICEID);
+ rev_id = pmic_reg_read(dev, PFUZE3000_REVID);
+ printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id);
+
+ /* disable Low Power Mode during standby mode */
+ reg = pmic_reg_read(dev, PFUZE3000_LDOGCTL);
+ reg |= 0x1;
+ pmic_reg_write(dev, PFUZE3000_LDOGCTL, reg);
+
+ /* SW1A/1B mode set to APS/APS */
+ reg = 0x8;
+ pmic_reg_write(dev, PFUZE3000_SW1AMODE, reg);
+ pmic_reg_write(dev, PFUZE3000_SW1BMODE, reg);
+
+ /* SW1A/1B standby voltage set to 0.975V */
+ reg = 0xb;
+ pmic_reg_write(dev, PFUZE3000_SW1ASTBY, reg);
+ pmic_reg_write(dev, PFUZE3000_SW1BSTBY, reg);
+
+ /* set SW1B normal voltage to 0.975V */
+ reg = pmic_reg_read(dev, PFUZE3000_SW1BVOLT);
+ reg &= ~0x1f;
+ reg |= PFUZE3000_SW1AB_SETP(975);
+ pmic_reg_write(dev, PFUZE3000_SW1BVOLT, reg);
+
+ return 0;
+}
+#endif
+
+int board_late_init(void)
+{
+#ifdef CONFIG_CMD_BMODE
+ add_board_boot_modes(board_boot_modes);
+#endif
+
+#ifdef CONFIG_ENV_IS_IN_MMC
+ board_late_mmc_env_init();
+#endif
+
+ imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
+
+ set_wdog_reset((struct wdog_regs *)WDOG1_BASE_ADDR);
+
+ return 0;
+}
+
+u32 get_board_rev(void)
+{
+ return get_cpu_rev();
+}
+
+int checkboard(void)
+{
+ puts("Board: MX7D 12x12 DDR3 ARM2\n");
+
+ return 0;
+}
diff --git a/board/freescale/mx7d_12x12_ddr3_arm2/plugin.S b/board/freescale/mx7d_12x12_ddr3_arm2/plugin.S
new file mode 100644
index 0000000..1bc05dc
--- /dev/null
+++ b/board/freescale/mx7d_12x12_ddr3_arm2/plugin.S
@@ -0,0 +1,217 @@
+/*
+ * Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <config.h>
+
+/* DDR script */
+.macro imx7d_ddrphy_latency_setting
+ ldr r2, =ANATOP_BASE_ADDR
+ ldr r3, [r2, #0x800]
+ and r3, r3, #0xFF
+ cmp r3, #0x11
+ bne NO_DELAY
+
+ /*TO 1.1*/
+ ldr r1, =0x00000dee
+ str r1, [r0, #0x9c]
+ ldr r1, =0x18181818
+ str r1, [r0, #0x7c]
+ ldr r1, =0x18181818
+ str r1, [r0, #0x80]
+ ldr r1, =0x40401818
+ str r1, [r0, #0x84]
+ ldr r1, =0x00000040
+ str r1, [r0, #0x88]
+ ldr r1, =0x40404040
+ str r1, [r0, #0x6c]
+ b TUNE_END
+
+NO_DELAY:
+ /*TO 1.0*/
+ ldr r1, =0x00000d6e
+ str r1, [r0, #0x9c]
+
+TUNE_END:
+.endm
+
+.macro imx7d_ddr_freq_setting
+ ldr r2, =ANATOP_BASE_ADDR
+ ldr r3, [r2, #0x800]
+ and r3, r3, #0xFF
+ cmp r3, #0x11
+ bne FREQ_DEFAULT_533
+
+ /* Change to 400Mhz for TO1.1 */
+ ldr r0, =ANATOP_BASE_ADDR
+ ldr r1, =0x70
+ ldr r2, =0x00703021
+ str r2, [r0, r1]
+ ldr r1, =0x90
+ ldr r2, =0x0
+ str r2, [r0, r1]
+ ldr r1, =0x70
+ ldr r2, =0x00603021
+ str r2, [r0, r1]
+
+ ldr r3, =0x80000000
+wait_lock:
+ ldr r2, [r0, r1]
+ and r2, r3
+ cmp r2, r3
+ bne wait_lock
+
+ ldr r0, =CCM_BASE_ADDR
+ ldr r1, =0x9880
+ ldr r2, =0x1
+ str r2, [r0, r1]
+
+FREQ_DEFAULT_533:
+.endm
+
+.macro imx7d_12x12_ddr3_arm2_ddr_setting
+ imx7d_ddr_freq_setting
+
+ /* Configure ocram_epdc */
+ ldr r0, =IOMUXC_GPR_BASE_ADDR
+ ldr r1, =0x4f400005
+ str r1, [r0, #0x4]
+
+ ldr r0, =SRC_BASE_ADDR
+ ldr r1, =0x2
+ ldr r2, =0x1000
+ str r1, [r0, r2]
+
+ ldr r0, =DDRC_IPS_BASE_ADDR
+ ldr r1, =0x03040001
+ str r1, [r0]
+ ldr r1, =0x80400003
+ str r1, [r0, #0x1a0]
+ ldr r1, =0x00100020
+ str r1, [r0, #0x1a4]
+ ldr r1, =0x80100004
+ str r1, [r0, #0x1a8]
+ ldr r1, =0x0040005e
+ str r1, [r0, #0x64]
+ ldr r1, =0x1
+ str r1, [r0, #0x490]
+ ldr r1, =0x00020001
+ str r1, [r0, #0xd0]
+ ldr r1, =0x00010000
+ str r1, [r0, #0xd4]
+ ldr r1, =0x09300004
+ str r1, [r0, #0xdc]
+ ldr r1, =0x04080000
+ str r1, [r0, #0xe0]
+ ldr r1, =0x00090004
+ str r1, [r0, #0xe4]
+ ldr r1, =0x33f
+ str r1, [r0, #0xf4]
+ ldr r1, =0x0908120a
+ str r1, [r0, #0x100]
+ ldr r1, =0x0002020e
+ str r1, [r0, #0x104]
+ ldr r1, =0x03040407
+ str r1, [r0, #0x108]
+ ldr r1, =0x00002006
+ str r1, [r0, #0x10c]
+ ldr r1, =0x04020204
+ str r1, [r0, #0x110]
+ ldr r1, =0x03030202
+ str r1, [r0, #0x114]
+ ldr r1, =0x03030803
+ str r1, [r0, #0x120]
+ ldr r1, =0x00800020
+ str r1, [r0, #0x180]
+ ldr r1, =0x02098204
+ str r1, [r0, #0x190]
+ ldr r1, =0x00030303
+ str r1, [r0, #0x194]
+
+ ldr r1, =0x00000016
+ str r1, [r0, #0x200]
+ ldr r1, =0x00171717
+ str r1, [r0, #0x204]
+ ldr r1, =0x04040404
+ str r1, [r0, #0x214]
+ ldr r1, =0x00040404
+ str r1, [r0, #0x218]
+
+ ldr r1, =0x06000601
+ str r1, [r0, #0x240]
+ ldr r1, =0x00001323
+ str r1, [r0, #0x244]
+
+ ldr r0, =SRC_BASE_ADDR
+ mov r1, #0x0
+ ldr r2, =0x1000
+ str r1, [r0, r2]
+
+ ldr r0, =DDRPHY_IPS_BASE_ADDR
+ ldr r1, =0x17420f40
+ str r1, [r0]
+ ldr r1, =0x10210100
+ str r1, [r0, #0x4]
+ ldr r1, =0x00060807
+ str r1, [r0, #0x10]
+ imx7d_ddrphy_latency_setting
+ ldr r1, =0x08080808
+ str r1, [r0, #0x20]
+ ldr r1, =0x08080808
+ str r1, [r0, #0x30]
+ ldr r1, =0x01000010
+ str r1, [r0, #0x50]
+
+ ldr r1, =0x0e407304
+ str r1, [r0, #0xc0]
+ ldr r1, =0x0e447304
+ str r1, [r0, #0xc0]
+ ldr r1, =0x0e447306
+ str r1, [r0, #0xc0]
+
+wait_zq:
+ ldr r1, [r0, #0xc4]
+ tst r1, #0x1
+ beq wait_zq
+
+ ldr r1, =0x0e447304
+ str r1, [r0, #0xc0]
+ ldr r1, =0x0e407304
+ str r1, [r0, #0xc0]
+
+ ldr r0, =CCM_BASE_ADDR
+ mov r1, #0x0
+ ldr r2, =0x4130
+ str r1, [r0, r2]
+ ldr r0, =IOMUXC_GPR_BASE_ADDR
+ mov r1, #0x178
+ str r1, [r0, #0x20]
+ ldr r0, =CCM_BASE_ADDR
+ mov r1, #0x2
+ ldr r2, =0x4130
+ str r1, [r0, r2]
+ ldr r0, =DDRPHY_IPS_BASE_ADDR
+ ldr r1, =0x0000000f
+ str r1, [r0, #0x18]
+
+ ldr r0, =DDRC_IPS_BASE_ADDR
+wait_stat:
+ ldr r1, [r0, #0x4]
+ tst r1, #0x1
+ beq wait_stat
+.endm
+
+.macro imx7_clock_gating
+.endm
+
+.macro imx7_qos_setting
+.endm
+
+.macro imx7_ddr_setting
+ imx7d_12x12_ddr3_arm2_ddr_setting
+.endm
+
+/* include the common plugin code here */
+#include <asm/arch/mx7_plugin.S>