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| author | Poonam Aggrwal <poonam.aggrwal@freescale.com> | 2011-02-07 17:17:28 +0530 |
|---|---|---|
| committer | Kumar Gala <galak@kernel.crashing.org> | 2011-04-04 09:24:42 -0500 |
| commit | 66c74fca18aab4c4182be486641d7a374689c4c3 (patch) | |
| tree | fe5db1cbbaf69695c37d8e783cfee0af67923b80 /board/freescale | |
| parent | 3313b20b950060723e6897870f793db7d3582084 (diff) | |
| download | u-boot-imx-66c74fca18aab4c4182be486641d7a374689c4c3.zip u-boot-imx-66c74fca18aab4c4182be486641d7a374689c4c3.tar.gz u-boot-imx-66c74fca18aab4c4182be486641d7a374689c4c3.tar.bz2 | |
powerpc/85xx: Optimized DDR settings for 800MT/s on P1/P2 RDB
Changed the following DDR timing parameters for 800Mt/s:
tRRT BL/2+1 to BL/2
tWWT BL/2+1 to BL/2
tWRT BL/2+1 to BL/2
tRWT BL/2+1 to BL/2
REFINT 6500ns to 7800ns
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'board/freescale')
| -rw-r--r-- | board/freescale/p1_p2_rdb/ddr.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/board/freescale/p1_p2_rdb/ddr.c b/board/freescale/p1_p2_rdb/ddr.c index 853044e..71c6088 100644 --- a/board/freescale/p1_p2_rdb/ddr.c +++ b/board/freescale/p1_p2_rdb/ddr.c @@ -74,13 +74,13 @@ DECLARE_GLOBAL_DATA_PTR; #define CONFIG_SYS_DDR_INTERVAL_667 0x0a280100 #define CONFIG_SYS_DDR_TIMING_3_800 0x00040000 -#define CONFIG_SYS_DDR_TIMING_0_800 0x55770802 +#define CONFIG_SYS_DDR_TIMING_0_800 0x00770802 #define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b6543 #define CONFIG_SYS_DDR_TIMING_2_800 0x0fa074d1 #define CONFIG_SYS_DDR_CLK_CTRL_800 0x02800000 #define CONFIG_SYS_DDR_MODE_1_800 0x00040852 #define CONFIG_SYS_DDR_MODE_2_800 0x00000000 -#define CONFIG_SYS_DDR_INTERVAL_800 0x0a280100 +#define CONFIG_SYS_DDR_INTERVAL_800 0x0c300100 fsl_ddr_cfg_regs_t ddr_cfg_regs_400 = { .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS, |