diff options
| author | York Sun <yorksun@freescale.com> | 2012-07-06 17:10:33 -0500 |
|---|---|---|
| committer | Andy Fleming <afleming@freescale.com> | 2012-07-06 17:30:33 -0500 |
| commit | 48f6a5c348453fc3ab33aaa91e5e4198a28678ff (patch) | |
| tree | f1adc995cec4ced7d867de36230f1aa600c4d216 /board/freescale | |
| parent | 1e9ea85f7dffe949ca5e4845e6336810c144e06d (diff) | |
| download | u-boot-imx-48f6a5c348453fc3ab33aaa91e5e4198a28678ff.zip u-boot-imx-48f6a5c348453fc3ab33aaa91e5e4198a28678ff.tar.gz u-boot-imx-48f6a5c348453fc3ab33aaa91e5e4198a28678ff.tar.bz2 | |
powerpc/mpc85xx: Ignore E bit for SVR_SOC_VER()
We don't care E bit of SVR in most cases. Clear E bit for SVR_SOC_VER().
This will simplify the coding. Use IS_E_PROCESSOR() to identify SoC with
encryption. Remove all _E entries from SVR list and CPU list.
Signed-off-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'board/freescale')
| -rw-r--r-- | board/freescale/p1010rdb/ddr.c | 6 | ||||
| -rw-r--r-- | board/freescale/p1010rdb/p1010rdb.c | 4 | ||||
| -rw-r--r-- | board/freescale/p1_p2_rdb/ddr.c | 6 |
3 files changed, 7 insertions, 9 deletions
diff --git a/board/freescale/p1010rdb/ddr.c b/board/freescale/p1010rdb/ddr.c index 36c8545..10c5a42 100644 --- a/board/freescale/p1010rdb/ddr.c +++ b/board/freescale/p1010rdb/ddr.c @@ -101,7 +101,7 @@ unsigned long get_sdram_size(void) cpu = gd->cpu; /* P1014 and it's derivatives support max 16it DDR width */ - if (cpu->soc_ver == SVR_P1014 || cpu->soc_ver == SVR_P1014_E) + if (cpu->soc_ver == SVR_P1014) ddr_size = (CONFIG_SYS_DRAM_SIZE / 2); else ddr_size = CONFIG_SYS_DRAM_SIZE; @@ -146,7 +146,7 @@ phys_size_t fixed_sdram(void) cpu = gd->cpu; /* P1014 and it's derivatives support max 16bit DDR width */ - if (cpu->soc_ver == SVR_P1014 || cpu->soc_ver == SVR_P1014_E) { + if (cpu->soc_ver == SVR_P1014) { ddr_cfg_regs.ddr_sdram_cfg |= SDRAM_CFG_16_BE; ddr_cfg_regs.cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS >> 1; ddr_cfg_regs.ddr_sdram_cfg &= ~0x00180000; @@ -238,7 +238,7 @@ void fsl_ddr_board_options(memctl_options_t *popts, cpu = gd->cpu; /* P1014 and it's derivatives support max 16it DDR width */ - if (cpu->soc_ver == SVR_P1014 || cpu->soc_ver == SVR_P1014_E) + if (cpu->soc_ver == SVR_P1014) popts->data_bus_width = DDR_DATA_BUS_WIDTH_16; for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { diff --git a/board/freescale/p1010rdb/p1010rdb.c b/board/freescale/p1010rdb/p1010rdb.c index 02ba740..dfeb86f 100644 --- a/board/freescale/p1010rdb/p1010rdb.c +++ b/board/freescale/p1010rdb/p1010rdb.c @@ -190,7 +190,7 @@ int board_eth_init(bd_t *bis) #endif #ifdef CONFIG_TSEC3 /* P1014 and it's derivatives do not support eTSEC3 */ - if (cpu->soc_ver != SVR_P1014 && cpu->soc_ver != SVR_P1014_E) { + if (cpu->soc_ver != SVR_P1014) { SET_STD_TSEC_INFO(tsec_info[num], 3); num++; } @@ -301,7 +301,7 @@ void ft_board_setup(void *blob, bd_t *bd) #endif /* P1014 and it's derivatives don't support CAN and eTSEC3 */ - if (cpu->soc_ver == SVR_P1014 || cpu->soc_ver == SVR_P1014_E) { + if (cpu->soc_ver == SVR_P1014) { fdt_del_flexcan(blob); fdt_del_node_and_alias(blob, "ethernet2"); } diff --git a/board/freescale/p1_p2_rdb/ddr.c b/board/freescale/p1_p2_rdb/ddr.c index 71c6088..916439c 100644 --- a/board/freescale/p1_p2_rdb/ddr.c +++ b/board/freescale/p1_p2_rdb/ddr.c @@ -204,8 +204,7 @@ phys_size_t fixed_sdram (void) cpu = gd->cpu; /* P1020 and it's derivatives support max 32bit DDR width */ - if (cpu->soc_ver == SVR_P1020 || cpu->soc_ver == SVR_P1020_E || - cpu->soc_ver == SVR_P1011 || cpu->soc_ver == SVR_P1011_E) { + if (cpu->soc_ver == SVR_P1020 || cpu->soc_ver == SVR_P1011) { ddr_size = (CONFIG_SYS_SDRAM_SIZE * 1024 * 1024 / 2); } else { ddr_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; @@ -232,8 +231,7 @@ phys_size_t fixed_sdram (void) strmhz(buf, ddr_freq)); /* P1020 and it's derivatives support max 32bit DDR width */ - if(cpu->soc_ver == SVR_P1020 || cpu->soc_ver == SVR_P1020_E || - cpu->soc_ver == SVR_P1011 || cpu->soc_ver == SVR_P1011_E) { + if (cpu->soc_ver == SVR_P1020 || cpu->soc_ver == SVR_P1011) { ddr_cfg_regs.ddr_sdram_cfg |= SDRAM_CFG_32_BE; ddr_cfg_regs.cs[0].bnds = 0x0000001F; } |