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| author | Ye Li <ye.li@nxp.com> | 2017-03-16 11:25:35 +0800 |
|---|---|---|
| committer | Ye Li <ye.li@nxp.com> | 2017-04-05 17:24:33 +0800 |
| commit | 41895cd598be6c4a64fc4fec521120e4962abc28 (patch) | |
| tree | 53232007f8de5e6cffe40188774c7305c231b7dc /board/freescale | |
| parent | a4d958d120d29f6f79e9023715a42bac582f4c76 (diff) | |
| download | u-boot-imx-41895cd598be6c4a64fc4fec521120e4962abc28.zip u-boot-imx-41895cd598be6c4a64fc4fec521120e4962abc28.tar.gz u-boot-imx-41895cd598be6c4a64fc4fec521120e4962abc28.tar.bz2 | |
MLK-14445-2 mx7ulp_evk: Add QSPI flash support
Porting the QSPI flash board support from v2016.03, and convert to use
DM QSPI driver.
Since we need to support QSPI at default in u-boot, change the default
DTS file to qspi enabled DTS.
Signed-off-by: Ye Li <ye.li@nxp.com>
Diffstat (limited to 'board/freescale')
| -rw-r--r-- | board/freescale/mx7ulp_evk/mx7ulp_evk.c | 35 |
1 files changed, 35 insertions, 0 deletions
diff --git a/board/freescale/mx7ulp_evk/mx7ulp_evk.c b/board/freescale/mx7ulp_evk/mx7ulp_evk.c index 3618715..d6c27db 100644 --- a/board/freescale/mx7ulp_evk/mx7ulp_evk.c +++ b/board/freescale/mx7ulp_evk/mx7ulp_evk.c @@ -13,6 +13,7 @@ DECLARE_GLOBAL_DATA_PTR; #define UART_PAD_CTRL (PAD_CTL_PUS_UP) +#define QSPI_PAD_CTRL1 (PAD_CTL_PUS_UP | PAD_CTL_DSE) int dram_init(void) { @@ -32,6 +33,36 @@ static void setup_iomux_uart(void) ARRAY_SIZE(lpuart4_pads)); } +#ifdef CONFIG_FSL_QSPI +#ifndef CONFIG_DM_SPI +static iomux_cfg_t const quadspi_pads[] = { + MX7ULP_PAD_PTB8__QSPIA_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX7ULP_PAD_PTB15__QSPIA_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX7ULP_PAD_PTB16__QSPIA_DATA3 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX7ULP_PAD_PTB17__QSPIA_DATA2 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX7ULP_PAD_PTB18__QSPIA_DATA1 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX7ULP_PAD_PTB19__QSPIA_DATA0 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), +}; +#endif + +int board_qspi_init(void) +{ + u32 val; +#ifndef CONFIG_DM_SPI + mx7ulp_iomux_setup_multiple_pads(quadspi_pads, ARRAY_SIZE(quadspi_pads)); +#endif + + /* enable clock */ + val = readl(PCC1_RBASE + 0x94); + + if (!(val & 0x20000000)) { + writel(0x03000003, (PCC1_RBASE + 0x94)); + writel(0x43000003, (PCC1_RBASE + 0x94)); + } + return 0; +} +#endif + int board_early_init_f(void) { setup_iomux_uart(); @@ -44,5 +75,9 @@ int board_init(void) /* address of boot parameters */ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; +#ifdef CONFIG_FSL_QSPI + board_qspi_init(); +#endif + return 0; } |